For the power amplifier used in CDMA cellular phones, the supply voltage is switched between high and low at a transmission power several decibels higher than 10 dBm using a DC-DC converter to improve operational efficiency. The longer the operation time under low supply voltage, the lower the current consumption of the cellular phone. In order to increase the output power under low supply voltage, we applied the 2nd harmonic-injection technique, which is useful for distortion compensation. With 2nd harmonic-injection, there is an inflectional power point. The distortion increases rapidly when output power goes beyond the inflectional power point. It is important to make this inflectional power point high in order to compensate for distortion in the high output-power region. We report here that the inflectional power point can be increased by connecting a 2nd harmonic short circuit to the drain terminal of the FET to which the 2nd harmonic for distortion compensation is injected. A prototype of the final stage of the power amplifier under a supply voltage of Vdd=1.5 V is presented. We report that applying a CDMA uplink signal, 1.5 dB higher output power and 12% higher drain efficiency is achieved compared when only 2nd harmonic injection is employed.

A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.

In this paper two algorithms for the synthesis and minimization of a CA (cellular array architecture) are proposed. Starting from a completely specified single-output switching function, our methods produce rectangularly shaped arrays of cells, interconnected in chains, with an effort to minimize the number of the produced chains (cascades). This kind of cellular topology is known throughout the bibliography as Maitra cellular arrays. The significance of those algorithms is underlined by the fact that this particular type of cellular architecture can be mapped to reversible circuits and gates (generalized Toffoli gates), which are the type of logic used in quantum circuits. The proposed methodologies include use of ETDDs (EXOR ternary decision diagrams), and switching function decompositions (including new types of boolean expansions).

This paper presents a novel approach to improving the IDDQ-based diagnosability of a CMOS circuit by dividing the circuit into independent partitions and using a separate power supply for each partition. This technique makes it possible to implement multiple IDDQ measurement points, resulting in improved IDDQ-based diagnosability. The paper formalizes the problem of partitioning a circuit for this purpose and proposes optimal and heuristic based solutions. The effectiveness of the proposed approach is demonstrated through experimental results.

A novel bias circuit providing a stable quiescent current for temperature and supply voltage variations is proposed and implemented to a W-CDMA MMIC power amplifier. The power amplifier with the proposed bias circuit has the quiescent current variation of only 6% for the -30 to 90 temperature change, and 8.5% for the 2.9 V to 3.1 V supply voltage change, and the variation of the power gain at the 28 dBm output power is less than 0.8 (0.05) dB for the 0.1 V of supply voltage (60 of temperature) variation.

Under the assumption that clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period can be determined if delays between registers are given. This minimum feasible clock period might be reduced if delays between some registers are increased by delay insertion. In this paper, we propose a delay insertion algorithm to reduce the minimum clock period. First, the proposed algorithm determines a clock schedule ignoring some constraints. Second, the algorithm inserts delays to recover ignored constraints according to the delay-slack and delay-demand of the obtained clock schedule. We show that the proposed algorithm achieves the minimum clock period by delay insertion if the delay of each element in the circuit is unique. Experiments show that the amount of inserting delay and computational time are smaller than the conventional algorithm.

Transferring the image information in analog form between the focal plane array (FPA) and the external electronics causes the disturbance of the outside noise. On-chip analog-to-digital (A/D) converter into the readout integrated circuit (ROIC) can eliminate the possibilities of the cross-talk of noise. Also, the information can be transported more efficiently in power in the digital domain compared to the analog domain. In designing on-chip A/D converter for cooled type high density infrared detector array, the most stringent requirements are power dissipation, number of bits, die area and throughput. In this study, pipelined type A/D converter was adopted because it has high operation speed characteristics with medium power consumption. Capacitor averaging technique and digital error correction for high resolution was used to eliminate the error which is brought out from the device mismatch. The readout circuit was fabricated using 0.6 µm CMOS process for 128 128 mid-wavelength infrared (MWIR) HgCdTe detector array. Fabricated circuit used direct injection type for input stage, and then S/N ratio could be maximized with increasing the integration capacitor. The measured performance of the 14 b A/D converter exhibited 0.2 LSB differential non-linearity (DNL) and 4 LSB integral non-linearity (INL). A/D converter had a 1 MHz operation speed with 75 mW power dissipation at 5 V. It took the die area of 5.6 mm2. It showed the good performance that can apply for cooled type high density infrared detector array.

To enable the use of passive transmission lines (PTLs) for the interconnection of single-flux-quantum (SFQ) circuits, we have implemented a driver and a receiver and have developed a method for designing SFQ circuits with passive interconnections. Basic components and properties of passive interconnections, such as the frequency characteristics of the driver and receiver, the PTL delay, and the crosstalk between PTLs, have been experimentally verified. Our developed components and design method have been applied to actual SFQ circuits, such as a 44 switch having block-to-block passive interconnections and a 22 switch having gate-to-gate passive interconnections. We have also shown the advantages of PTLs over Josephson transmission lines (JTLs). We also discuss the prospects of SFQ circuits having passive interconnections.

This paper presents a novel wide tuning range CMOS Voltage Controlled Oscillator (VCO). VCO uses an on-chip variable inductor as an additional variable element to extend the tuning range of VCO. The fabricated variable inductor achieves the variable range of 35%. The VCO was fabricated using 0.35 µm standard CMOS process, and can be tuned continuously from 2.13 GHz to 3.28 GHz (tuning range of 38%) without degradation of phase noise. Wide tunable LC-VCO using a variable inductor is one of the key circuits for reconfigurable RF circuit.

An equivalent MOSFET circuit with a wide input range is proposed. The proposed circuit is suitable for a realization of a wide input range under a low power supply voltage. The circuit consists of a MOSFET array and level shift circuits. The sum of drain currents of the MOSFET array is used as an equivalent drain current. The equivalent drain current is represented by K(VGS-VT)2 even when its drain-to-source voltage is quite small and some MOSFETs in the array are in the non-saturation region or the cut-off region. The input range of the proposed circuit realized by k-MOSFET array is k times as wide as that of a single MOSFET. It is confirmed through HSPICE simulations that the proposed circuit is effective in applications with a wide dynamic range.

In this paper, we describe an accelerative current-programming method for active matrix OLED (AM-OLED) display. This new method uses common source configuration, "Acceleration Control" line and some mechanisms to prevent the programming current from flowing through OLED device. It would solve the basic problem of the current-programming pixel circuit: a long programming period, especially at the dark gray-level. The proposed method accelerates the current programming process at any gray levels, and it would be the solution for the problem.

We have fabricated a multilayer structure for single flux quantum (SFQ) circuit application using a high-temperature superconductor (HTS). La0.2-Y0.9Ba1.9Cu3Ox (La-YBCO) base electrode layers were prepared by a dc or rf magnetron sputtering method. The reproducibility of film quality for dc-sputtered La-YBCO films was better than that for rf-sputtered films, and the dc sputtered films exhibited the average surface roughness Ra less than 1.0 nm and a Tc zero value of 88 K. By using the dc-sputtered La-YBCO films, a multilayer structure of SrSnO3/La-YBCO/SrSnO3/La-YBCO on MgO substrate with Ra below 2.0 nm was obtained. Interface-modified ramp-edge junctions with La0.2-Yb0.9Ba1.9Cu3Ox (La-YbBCO) counter electrodes have been fabricated by using this multilayer structure with dc-sputtered films. The fabricated junctions exhibited RSJ-type I-V characteristics with IcRn products of about 3 mV at 4.2 K. We also obtained a 1-σ Ic spread of 8% for a 1000-junction series-array. The sheet inductance values at 4.2 K for the base and counter electrodes on La-YBCO ground planes were 0.8 pH and 0.7 pH per square, respectively. Operation of several types of elementary SFQ circuits has been successfully demonstrated by using this multilayer structure.

A design optimization of active shield circuit using noise averaging method is proposed. The relation between the averaged noise and the design parameters of the active shield circuit such as circuit gain and on-chip layout is examined. A simple design guideline is also provided. Simulation results show that the active shield circuit designed by the proposed optimization method gives a better noise suppression performance of about 28% than the conventional one.

In this paper, we propose a new algorithm for calculating the exact poles of the admittance matrix of RLCG interconnects. After choosing dominant poles and corresponding residues, each element of the exact admittance matrix is approximated by partial fraction. A procedure to obtain the residues that guarantee the passivity is also provided, based on experimental studies. In the procedure the residues are calculated by using the least squares method so that the partial fraction matches each element of the exact admittance matrix in the frequency-domain. From the partial fraction representation, the asymptotic equivalent circuit models which can be easily simulated with SPICE are synthesized. It is shown that an efficient model-order reduction is possible for short-length interconnects.

An active shield circuit which effectively reduces the substrate noise on the entire area inside the guard ring regardless of the noise source position is proposed. Simulation result shows that the proposed circuit can reduce the noise level to -85 dB while a conventional guard ring gives -52 dB.

This paper presents 160-Gbit/s full channel time-division demultiplexing using a semiconductor optical amplifier hybrid integrated demultiplexer on a planer lightwave circuit. Error-free demultiplexing from a 160-Gbit/s signal to 8 channel 20 Gbit/s signals is successfully demonstrated. Results of a 160-Gbit/s optical time-division-multiplexed full channel OTDM signal transmission experiment using the circuit and successful 80-km transmission are presented.

A mode transformer between the NRD guide and the vertical strip line was developed and applied to the right angle corner, T-junction, and 3-port junction at 60 GHz. Emphasis was placed on a fully CAD-based design procedure by using an electromagnetic field simulator. Agreement between the simulated and measured performances of the junction circuit was obtained, and thus the validity of the design procedure was confirmed. A well-balanced transmission coefficient of the 3-port junction, found to be 4 0.5 dB, was observed in the bandwidth of 2 GHz around a center frequency of 60 GHz.

This paper presents a design procedure of a directional coupler consisting of a twofold symmetric four-port circuit with four identical matching networks at each port. The intrinsic power-split ratio and the equivalent admittance of the directional coupler are formularized in terms of the eigenadmittances of the original four-port without the matching networks. These formulas are useful for judgment on the realizability of a directional coupler in a given circuit structure and for design of the matching networks. Actually, the present procedure is applied to designing various quadrature hybrids and directional couplers, and its practical usefulness as well as several new circuit structures are demonstrated.

Cryptosystems for smartcard are required to provide protection from Differential Power Analysis (DPA) attack. Self-timed circuit based cryptosystems demonstrate considerable resistance against DPA attack, but they take substantial circuit area. A novel approach offering up to 30% area reduction and maintaining DPA protection level close to DIMS scheme is proposed.

A new bipolar linear transconductor for low-voltage low-power signal processing is proposed. The proposed circuit has larger input linear range and smaller power dissipation when compared with the conventional bipolar linear transconductor. The experimental results show that the transconductor with a transconductance of 50 µS has a linearity error of less than 0.02% over an input voltage range of 2.1 V at supply voltages of 3 V. The power dissipation of the transconductor is 3.15 mW.