This paper presents an automatic synthesis method of active analog circuits that uses evolutionary search and employs some topological features of analog integrated circuits. Our system firstly generates a set of circuits at random, and then evolves their topologies and device sizing to fit an environment which is formed by the fitness function translated from the electrical specifications of the circuit. Therefore expert knowledge about circuit topologies and sizing are not needed. The capability of this method is demonstrated through experiments of automatic synthesis of CMOS operational amplifiers.

This paper presents improved versions of three-stage positive-output and two-stage negative-output Dickson charge-pump circuits which are intended to replace switching regulators in video-product CCD driver applications (where 12 V and -6.5 V are needed), and are designed and fabricated in a custom CMOS process. From a power supply Vdd of 4.0 to 5.5 V, the positive charge pump generates a positive output voltage of greater than 3.9Vdd, while the negative charge pump generates a negative voltage of greater than -1.9Vdd, both with efficiencies of greater than 94% at 2 mA output currents.

The analysis of the radiating properties of a multilayer structure where chirality is introduced is here addressed. Both the effects on the resonant behaviour and on the radiation patterns have been considered for different multilayer structures. The adopted procedure is full wave and leads to the numerical analysis performed via the Methods of Moment in the spectral domain.

In this paper, a high-speed PLA based on dynamic array logic circuits with latch sense amplifiers is presented. The present circuit consists of logic cell arrays, dual-rail bit-lines, latch sense amplifiers, and control blocks. By using a charge sharing scheme and latch sense amplifiers, voltage swings of the bit-lines are reduced compared to the conventional circuits, thus a high-speed and low-power operation is achieved. The present array logic configuration can realize any logic function expressed in the sum-of-products form by using PLA structure. As an application of the proposed PLA, a 32-bit binary comparator is designed and implemented in a 0.6-µm double-poly triple-metal CMOS process. Results of HSPICE simulation show a better performance compared to the conventional circuits. Functional testing using electron beam probing shows that the present circuit operates correctly.

Electric beam scanning reflector antennas provide beam scanning and pattern control, and can create narrow beams efficiently. However, they are not popular because the beam control circuit is large and difficult to realize. This paper proposes a new BFN configuration for cluster feeding of highly functional scanning antenna. The Enhanced PAttern Control nonswiTch (EPACT) BFN simplifies the beam control circuit and its control algorithm by using a fast Fourier transform (FFT) circuit, phase shifters, and a power divider. Furthermore, this paper proposes a design technique that uses modules to implement the FFT circuit and a method that optimizes amplifier placement to improve antenna efficiency. The design technique facilitates the manufacture of large-scale FFT circuits. The optimized amplifier location improves the antenna efficiency by eliminating the partial concentration of signal power.

We show some results concerning the number of solutions of the equation y+Ax=b (yTx=0, y0, x0) which plays a central role in the dc analysis of transistor circuits. In particular, we give sufficient conditions for the equation to possess exactly 2l (ln) solutions, where n is the dimension of the vector x.

This letter presents a method for reducing power dissipation in a protocol converter. The communication protocol of a VLSI chip hierarchically consists of several sub-protocols and only one of them can be actively working at any given time. In general, protocol converters are implemented by dual protocols of the initially given protocols which are to be interfaced. If the duals of those sub-protocols are implemented in separate modules, we can separate active modules and inactive modules on the fly since only one of the modules can be active at a time. The active/inactive state of a module can be monitored by the control signals that represent the execution of the protocol corresponding to the module. Power reduction can be achieved by dynamically suppressing the clock supply to inactive modules. To trade-off the power reduction rate against the area overhead, the module granularity must be properly chosen. For this purpose, we implement the duals of the atomic protocols in the same module if their state graphs share states except the initial state. Our experimental results show that this method provides significant savings in power consumption of between 18.4% and 92.1% with a 5.3% area overhead.

In this paper, we propose an approach to test pattern generation for Speed-Independent (SI) asynchronous control circuits. Test patterns are generated based on a specified sequence, which is derived from the specification of a target circuit in the form of a Signal Transition Graph (STG). Since the sequence represents the behavior of a circuit only with stable states, the state space of the circuit can be represented as reduced one. A product machine, which consists of a fault-free circuit and a faulty circuit, is constructed and then the specified sequence is applied sequentially to the product machine. A fault is detected when the product machine produces inconsistency, i.e., output values of a fault-free circuit and a faulty circuit are different, and the sequentially applied part of the sequence becomes a test pattern to detect the fault. We also propose a test generation method using an undetectable fault identification as well as the specified sequence. Since the reduced state space is a subset of that of a gate level implementation, test patterns based on a specification cannot detect some faults. The proposed method identifies those faults with a circuit topology in advance. BDD is used to implement the proposed methods efficiently, since the proposed methods have a lot of state sets and set operations. Experimental results show that the test generation using a specification achieves high fault coverage over single stuck-at fault model for several synthesized SI circuits. The proposed test generation using a circuit topology as well as a specification decreases execution time for test generation with negligible cost retaining high fault coverage.

In the circuit-switching literature, the Least Loaded Path Routing (LLR) concept has been shown to be very simple and efficient. However, it seems that there is no unique definition for the "least busy" path, i.e., how to measure the degree of "busy" of a path. In this paper, we examine six ways of defining the least busy path and a random policy. The performance of these policies is evaluated via both simulation and analysis. Our numerical results show that all policies, include the random policy, have almost the same performance under most of the network configurations. Only under extremely low traffic load conditions, the difference between the policies becomes significant. However, the magnitude of the difference is still very small (about 0.001). Therefore, we conclude that how to select the alternate path does not affect the performance of LLR-based routing algorithms significantly when the call blocking probability is not too small. Instead, we found that the trunk reservation level affects the performance of LLR-based routing algorithms significantly.

Photonic crystals have seen major advances in the past few years in the optical range. The association of in-plane waveguiding and two-dimensional photonic crystals (PCs) in thin-slab or waveguide structures leads to good 3D confinement with easy fabrication. Such structures, much easier to fabricate than 3D PCs open many exciting opportunities in optoelectronic devices and integrated optics. We present experiments on a variety of structures and devices, as well as modelling tools, which show that 2D PCs etched through waveguides supported by substrates are a viable route to high-performance PC-based photonic integrated circuits (PICs). In particular, they exhibit low out-of-plane diffraction losses. Low-loss waveguides, high finesse microcavities, and their mutual coupling are demonstrated. PACS: 42.70 QS, 42.55 Sa, 42.82 m, 42.50-p.

A wavelength demultiplexer made of 2-D photonic crystal capable of simultaneously separating many channels from WDM light is analyzed in order to study the properties and clarify the design parameters. Numerical analyses are carried out for the optical filter structure and the demultiplexer structure which consists of several filters and waveguides carved in the crystal. The results of this paper show the considerations regarding the frequency tuning, the device size, the bandwidth and integration of filters. Further more, for a photonic crystal filter, a method for realizing a flat-top pass-band generally required from the dense-WDM systems is presented and its property is shown. The calculation method is the scattering matrix method which is proper to the analysis of the frequency domain in a 2-D photonic crystal with finite size and with some defects.

The effect of wavelength detuning on the device performance of identical-epitaxial-layer (IEL) electroabsorption (EA) modulator integrated distributed feedback (DFB) lasers is studied in detail. Based on the lasing behavior of integrated devices with different amount of wavelength detuning and the photocurrent spectra under different reverse biases, the optimal wavelength detuning is experimentally determined to be around 30-40 nm for our IEL integrated devices. By adopting gain-coupled DFB laser section, integrated devices with optimal wavelength detuning have demonstrated excellent single mode performances. The extinction ratio is measured to be greater than 15 dB at -3 V, and the modulation bandwidth is around 8 GHz.

The effect of wavelength detuning on the device performance of identical-epitaxial-layer (IEL) electroabsorption (EA) modulator integrated distributed feedback (DFB) lasers is studied in detail. Based on the lasing behavior of integrated devices with different amount of wavelength detuning and the photocurrent spectra under different reverse biases, the optimal wavelength detuning is experimentally determined to be around 30-40 nm for our IEL integrated devices. By adopting gain-coupled DFB laser section, integrated devices with optimal wavelength detuning have demonstrated excellent single mode performances. The extinction ratio is measured to be greater than 15 dB at -3 V, and the modulation bandwidth is around 8 GHz.

We improve the algorithm to obtain the min-cut graph of a hyper-graph and show an application to the sub-network extraction problem. The min-cut graph is a directed acyclic graph whose directed cuts correspond one-to-one to the min-cuts of the hyper-graph. While the known approach trades the exactness of the min-cut graph for some speed improvement, our proposed algorithm gives an exact one without substantial computation overhead. By using the exact min-cut graph, an exhaustive algorithm finds an optimal sub-circuit that is extracted by a min-cut from the circuit. By experiments with the industrial data, the proposing method showed a performance enough for practical use.

A wavelength demultiplexer made of 2-D photonic crystal capable of simultaneously separating many channels from WDM light is analyzed in order to study the properties and clarify the design parameters. Numerical analyses are carried out for the optical filter structure and the demultiplexer structure which consists of several filters and waveguides carved in the crystal. The results of this paper show the considerations regarding the frequency tuning, the device size, the bandwidth and integration of filters. Further more, for a photonic crystal filter, a method for realizing a flat-top pass-band generally required from the dense-WDM systems is presented and its property is shown. The calculation method is the scattering matrix method which is proper to the analysis of the frequency domain in a 2-D photonic crystal with finite size and with some defects.

Photonic crystals have seen major advances in the past few years in the optical range. The association of in-plane waveguiding and two-dimensional photonic crystals (PCs) in thin-slab or waveguide structures leads to good 3D confinement with easy fabrication. Such structures, much easier to fabricate than 3D PCs open many exciting opportunities in optoelectronic devices and integrated optics. We present experiments on a variety of structures and devices, as well as modelling tools, which show that 2D PCs etched through waveguides supported by substrates are a viable route to high-performance PC-based photonic integrated circuits (PICs). In particular, they exhibit low out-of-plane diffraction losses. Low-loss waveguides, high finesse microcavities, and their mutual coupling are demonstrated. PACS: 42.70 QS, 42.55 Sa, 42.82 m, 42.50-p.

This paper proposes an efficient reduction method for a substrate network model, which is extracted from layout data, to analize a substrate coupling noise. The proposed method adopts in a reduction operation a hierarchic structure of a substrate RC network model, a computational procedure using matrix elements, and an expression of admittance as polynominal in complex frequency s=jω. These techniques improve computational efficiency and are suitable for an implementation. In the example of a triple well CMOS circuit, a reduced model, from 7500 nodes to 5 nodes, has less than 25% errors up to 1 GHz.

In this report, a design method of neural networks for limit cycle generator is described. First, the constraint conditions for the synaptic weights, which are given by the linear inequalities, are derived from the dynamics of neural networks. Next, the linear inequalities are solved by the linear programming method. The synaptic weights and other parameters are determined by the above solutions. Furthermore, neuro-based limit cycle generator is designed with analog electronic circuits and simulated by Spice. Finally, we confirm that our design method is efficient and practical for the design of neuro-based limit cycle generator.

A merged analog-digital circuit architecture is proposed for implementing intelligence in SoC systems. Pulse modulation signals are introduced for time-domain massively parallel analog signal processing, and also for interfacing analog and digital worlds naturally within the SoC VLSI chip. Principles and applications of pulse-domain linear arithmetic processing are explored, and the results are expanded to the nonlinear signal processing, including an arbitrary chaos generation and continuous-time dynamical systems with nonlinear oscillation. Silicon implementations of the circuits employing the proposed architecture are fully described.

We have proposed a current-cut switched-current matched filter (CC-SIMF) for direct-sequence code-division multiple-access (DS-CDMA). The 256-chip CC-SIMF can achieve low power consumption of less than 10 mW under high-speed operation of more than 16 Mcps. To reduce the current transfer error accumulation, we propose a parallel SIMF configuration. A 128-chip SIMF using 0.8-µm Complementally Metal Oxide Semiconductor (CMOS) process has been designed and fabricated. Optimization of the current memory cell structure has been described. The correlation operation at 16 Mcps has been obtained using a 128-chip orthogonal m-sequence. The code phase separation performance for path diversity has been clearly observed. The power consumption has been significantly reduced using the current-cut method.