IEICE TRANSACTIONS on Fundamentals
An Efficient Reduction Method of a Substrate RC Network Model
Summary :
This paper proposes an efficient reduction method for a substrate network model, which is extracted from layout data, to analize a substrate coupling noise. The proposed method adopts in a reduction operation a hierarchic structure of a substrate RC network model, a computational procedure using matrix elements, and an expression of admittance as polynominal in complex frequency s=jω. These techniques improve computational efficiency and are suitable for an implementation. In the example of a triple well CMOS circuit, a reduced model, from 7500 nodes to 5 nodes, has less than 25% errors up to 1 GHz.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.3 pp.698-704
- Publication Date
- 2001/03/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Tomohisa KIMURA, Makiko OKUMURA, "An Efficient Reduction Method of a Substrate RC Network Model" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 3, pp. 698-704, March 2001, doi: .
Abstract: This paper proposes an efficient reduction method for a substrate network model, which is extracted from layout data, to analize a substrate coupling noise. The proposed method adopts in a reduction operation a hierarchic structure of a substrate RC network model, a computational procedure using matrix elements, and an expression of admittance as polynominal in complex frequency s=jω. These techniques improve computational efficiency and are suitable for an implementation. In the example of a triple well CMOS circuit, a reduced model, from 7500 nodes to 5 nodes, has less than 25% errors up to 1 GHz.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_3_698/_p
Copy
@ARTICLE{e84-a_3_698,
author={Tomohisa KIMURA, Makiko OKUMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={An Efficient Reduction Method of a Substrate RC Network Model},
year={2001},
volume={E84-A},
number={3},
pages={698-704},
abstract={This paper proposes an efficient reduction method for a substrate network model, which is extracted from layout data, to analize a substrate coupling noise. The proposed method adopts in a reduction operation a hierarchic structure of a substrate RC network model, a computational procedure using matrix elements, and an expression of admittance as polynominal in complex frequency s=jω. These techniques improve computational efficiency and are suitable for an implementation. In the example of a triple well CMOS circuit, a reduced model, from 7500 nodes to 5 nodes, has less than 25% errors up to 1 GHz.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - An Efficient Reduction Method of a Substrate RC Network Model
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 698
EP - 704
AU - Tomohisa KIMURA
AU - Makiko OKUMURA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2001
AB - This paper proposes an efficient reduction method for a substrate network model, which is extracted from layout data, to analize a substrate coupling noise. The proposed method adopts in a reduction operation a hierarchic structure of a substrate RC network model, a computational procedure using matrix elements, and an expression of admittance as polynominal in complex frequency s=jω. These techniques improve computational efficiency and are suitable for an implementation. In the example of a triple well CMOS circuit, a reduced model, from 7500 nodes to 5 nodes, has less than 25% errors up to 1 GHz.
ER -
English
