A substrate coupling simulation method suitable for execution in a conventional CAD environment is proposed. In this method, a substrate network is extracted from the layout data, and analyses are carried out using a circuit simulator in a conventional CAD environment. Substrate model simplification techniques are adopted for efficient analysis. Test chips were fabricated in order to compare the simulated results with the measured results. The comparison confirmed the effectiveness of the proposed simulation method.

A novel learning algorithm for a neural network LSI which has low resolution synapse weights is proposed. Following a brief discussion of the synapse weight adaptation mechanism in the gradient descent scheme, we propose a way of achieving relaxation from the influence of discretized weight. Restriction of the number of synapses to be updated in one learning iteration is effective to relax the influence. Simulation results support the effectiveness of this learning algorithm. Low resolution synapses will be practical to realize large-scale neural network LSIs.

In this paper we propose a new method for removing the characteristic of the piezoelectric transducer from the received signal in the pulse-echo method so that the time resolution in the determination of transit time of ultrasound in a thin layer is increased. The total characteristic of the pulse-echo system is described by cascade of distributed-constant systems for the ultrasonic transducer, matching layer, and acoustic medium. The input impedance is estimated by the inverse matrix of the cascade system and the voltage signal at the electrical port. From the inverse Fourier transform of input impedance, the transit time in a thin layer object is accurately determined with high time resolution. The principle of the method is confirmed by simulation experiments.

This paper proposes an efficient reduction method for a substrate network model, which is extracted from layout data, to analize a substrate coupling noise. The proposed method adopts in a reduction operation a hierarchic structure of a substrate RC network model, a computational procedure using matrix elements, and an expression of admittance as polynominal in complex frequency s=jω. These techniques improve computational efficiency and are suitable for an implementation. In the example of a triple well CMOS circuit, a reduced model, from 7500 nodes to 5 nodes, has less than 25% errors up to 1 GHz.