Substrate noise coupling in RF receiver front-end circuitry for LTE wireless communication was examined by full-chip level simulation and on-chip measurements, with a demonstrator built in a 65nm CMOS technology. A CMOS digital noise emulator injects high-order harmonic noises in a silicon substrate and induces in-band spurious tones in an RF receiver on the same chip through substrate noise interference. A complete simulation flow of full-chip level substrate noise coupling uses a decoupled modeling approach, where substrate noise waveforms drawn with a unified package-chip model of noise source circuits are given to mixed-level simulation of RF chains as noise sensitive circuits. The distribution of substrate noise in a chip and the attenuation with distance are simulated and compared with the measurements. The interference of substrate noise at the 17th harmonics of 124.8MHz — the operating frequency of the CMOS noise emulator creates spurious tones in the communication bandwidth at 2.1GHz.

This paper presents measurement of on-chip coupling between PA and LNA integrated on Si CMOS substrate, which is caused by substrate coupling, magnetic coupling, power-line coupling, etc. These components are decomposed by measurements using diced chips. The result reveals that the substrate coupling is the most dominant in CMOS chips and the total isolation becomes less than -50 dB with more than 0.4 mm PA-to-LNA distance.

An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.

Capacitance charging modeling efficiently captures power supply currents in dynamic operations of a CMOS digital circuit and accurately expresses their interaction with on- and off-chip impedance networks. Derivation of such models is generally defined for combinational and sequential logic functions. Simulated substrate and power noises due to sequential logic operation show clear dependency on the size of circuits as well as the internal activity of logic gates. Furthermore, it is experimentally found that the inclusion of impedance networks of a silicon substrate, a package, and an evaluation board, is substantially effective to improve the accuracy of noise analysis. Quantitative correlation among simulation with on-chip noise measurements is demonstrated in a 90-nm 1.2-V CMOS technology.

Chip-level substrate coupling analysis uses F-matrix computation with slice-and-stack execution to include highly concentrated substrate resistivity gradient. The technique that has been applied to evaluation of device-level isolation structures against substrate coupling is now developed into chip-level substrate noise analysis. A time-series divided parasitic capacitance (TSDPC) model is equivalent to a transition controllable noise source (TCNS) circuit that captures noise generation in a CMOS digital circuit. A reference structure incorporating TCNS circuits and an array of on-chip high precision substrate noise monitors provides a basis for the verification of chip-level analysis of substrate coupling in a given technology. Test chips fabricated in two different wafer processings of 0.30-µm and 0.18-µm CMOS technologies demonstrate the universal availability of the proposed analysis techniques. Substrate noise simulation achieves no more than 3 dB discrepancy in peak amplitude compared to measurements with 100-ps/100-µV resolution, enabling precise evaluation of the impacts of the distant placements of sensitive devices from sources of noise as well as application of guard ring/band structures.

Substrate-coupling equivalent circuits can be derived for arbitrary isolation structures by F-matrix computation. The derived netlist represents a unified impedance network among multiple sites on a chip surface as well as internal nodes of isolation structures and can be applied with SPICE simulation to evaluate isolation strengths. Geometry dependency of isolation attributes to layout parameters such as area, width, and location distance. On the other hand, structural dependency arises from vertical impurity concentration specific to p+/n+ diffusion and deep n-well. Simulation-based prototyping of isolation structures can include all these dependences and strongly helps establish an isolation strategy against high-frequency substrate coupling in a given technology. The analysis of isolation strength provided by p+/n+ guard ring, deep n-well guard ring as well as deep n-well pocket well explains S21 measurements performed on high-frequency test structures targeting 5 GHz bandwidth, that was formed in a 0.25-µm CMOS high frequency.

A feedforward-based active shielding technique for digital noise suppression is more preferred for its capability of reducing the noise on the entire area inside the guard ring. In order to compensate for the variation of substrate parameters, an automatic control scheme to tune the gain of the active shield circuit is proposed. Simulation results show the effectiveness of the proposed system in reducing the digital noise regardless of circuit layout. Simulation results also show that noise suppression improvement from passive guard ring to active shield with tuning is 20 dB or one tenth while that from active shield without tuning to active shield with tuning is 12 dB.

A GPS radio design for a complete single chip GPS receiver using 0.18-µm CMOS is presented. The complete single chip GPS receiver satisfies several key requirements for mobile applications, such as compactness, low power, and high sensitivity. The radio part, including the RF front end, the RF/IF PLLs, and IF functions, occupies 2.0 2.3 mm in a total chip area of 6.3 6.3 mm. It is fabricated using 0.18-µm CMOS technology utilizing MIM capacitors. The radio part operates within a 1.6 to 2.0 V supply voltage range and consumes 27 mW at 1.8 V. The whole GPS SoC consumes 57 mW for a fully functional chip and provides a high sensitivity of -152 dBm. The radio design features countermeasures against substrate coupling noise from the digital part.

An active shield circuit which effectively reduces the substrate noise on the entire area inside the guard ring regardless of the noise source position is proposed. Simulation result shows that the proposed circuit can reduce the noise level to -85 dB while a conventional guard ring gives -52 dB.

A design optimization of active shield circuit using noise averaging method is proposed. The relation between the averaged noise and the design parameters of the active shield circuit such as circuit gain and on-chip layout is examined. A simple design guideline is also provided. Simulation results show that the active shield circuit designed by the proposed optimization method gives a better noise suppression performance of about 28% than the conventional one.

A substrate coupling simulation method suitable for execution in a conventional CAD environment is proposed. In this method, a substrate network is extracted from the layout data, and analyses are carried out using a circuit simulator in a conventional CAD environment. Substrate model simplification techniques are adopted for efficient analysis. Test chips were fabricated in order to compare the simulated results with the measured results. The comparison confirmed the effectiveness of the proposed simulation method.

This paper describes fully integrated active guard band filters for suppressing the substrate coupling noise and their noise suppression effect measured by test chip experiments. The noise cancellation circuit of the active guard band filters simply consists of an inverter and a source follower. The substrate noise suppression effect was measured by using a test chip fabricated in a 0.18 µm CMOS triple-well process for system-on-a-chip. The noise with the filter was less than 5% of that without the filter and the noise suppression effect was observed from 1 MHz to 200 MHz by the statistical measurement of the voltage comparator. The noise suppression effect was also observed for actual digital switching noise produced by digital inverters. Configuration of the active guard band filter was investigated by simulation and it is shown that high and uniform noise suppression effect is achieved by placing the guard bands in the L-shape around the target triple-well area on the p-substrate.

A fully on-chip active guard band circuit is proposed. The proposed circuit is mainly composed of current mirrors and based on a DC bias technique. HSPICE simulations and experiment results confirm the validity of the proposed active guard band circuit.

This paper proposes an efficient reduction method for a substrate network model, which is extracted from layout data, to analize a substrate coupling noise. The proposed method adopts in a reduction operation a hierarchic structure of a substrate RC network model, a computational procedure using matrix elements, and an expression of admittance as polynominal in complex frequency s=jω. These techniques improve computational efficiency and are suitable for an implementation. In the example of a triple well CMOS circuit, a reduced model, from 7500 nodes to 5 nodes, has less than 25% errors up to 1 GHz.

An AC coupling configuration for the active guard band filters is introduced for suppressing substrate coupling noise in analog and digital mixed-signal integrated circuits. With this method, a substrate-coupling-noise cancellation signal can be supplied to a ground-level substrate by using a single 3-V supply on-chip circuits. Noise was suppressed to a maximum of less than 0.05 from 100 Hz to 2 MHz in a 0.35-µm CMOS test chip. Both experiments and a simulation based on the substrate extraction model showed the similar dependence of the noise-suppression effect on the arrangement of the guard-bands and analog circuits. The simulation is thus effective for optimizing the arrangement to suppress noise effects when designing a chip.