Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits
Summary :
Capacitance charging modeling efficiently captures power supply currents in dynamic operations of a CMOS digital circuit and accurately expresses their interaction with on- and off-chip impedance networks. Derivation of such models is generally defined for combinational and sequential logic functions. Simulated substrate and power noises due to sequential logic operation show clear dependency on the size of circuits as well as the internal activity of logic gates. Furthermore, it is experimentally found that the inclusion of impedance networks of a silicon substrate, a package, and an evaluation board, is substantially effective to improve the accuracy of noise analysis. Quantitative correlation among simulation with on-chip noise measurements is demonstrated in a 90-nm 1.2-V CMOS technology.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E93-A No.2 pp.440-447
- Publication Date
- 2010/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E93.A.440
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
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Tetsuro MATSUNO, Daisuke KOSAKA, Makoto NAGATA, "Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E93-A, no. 2, pp. 440-447, February 2010, doi: 10.1587/transfun.E93.A.440.
Abstract: Capacitance charging modeling efficiently captures power supply currents in dynamic operations of a CMOS digital circuit and accurately expresses their interaction with on- and off-chip impedance networks. Derivation of such models is generally defined for combinational and sequential logic functions. Simulated substrate and power noises due to sequential logic operation show clear dependency on the size of circuits as well as the internal activity of logic gates. Furthermore, it is experimentally found that the inclusion of impedance networks of a silicon substrate, a package, and an evaluation board, is substantially effective to improve the accuracy of noise analysis. Quantitative correlation among simulation with on-chip noise measurements is demonstrated in a 90-nm 1.2-V CMOS technology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E93.A.440/_p
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@ARTICLE{e93-a_2_440,
author={Tetsuro MATSUNO, Daisuke KOSAKA, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits},
year={2010},
volume={E93-A},
number={2},
pages={440-447},
abstract={Capacitance charging modeling efficiently captures power supply currents in dynamic operations of a CMOS digital circuit and accurately expresses their interaction with on- and off-chip impedance networks. Derivation of such models is generally defined for combinational and sequential logic functions. Simulated substrate and power noises due to sequential logic operation show clear dependency on the size of circuits as well as the internal activity of logic gates. Furthermore, it is experimentally found that the inclusion of impedance networks of a silicon substrate, a package, and an evaluation board, is substantially effective to improve the accuracy of noise analysis. Quantitative correlation among simulation with on-chip noise measurements is demonstrated in a 90-nm 1.2-V CMOS technology.},
keywords={},
doi={10.1587/transfun.E93.A.440},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 440
EP - 447
AU - Tetsuro MATSUNO
AU - Daisuke KOSAKA
AU - Makoto NAGATA
PY - 2010
DO - 10.1587/transfun.E93.A.440
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E93-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2010
AB - Capacitance charging modeling efficiently captures power supply currents in dynamic operations of a CMOS digital circuit and accurately expresses their interaction with on- and off-chip impedance networks. Derivation of such models is generally defined for combinational and sequential logic functions. Simulated substrate and power noises due to sequential logic operation show clear dependency on the size of circuits as well as the internal activity of logic gates. Furthermore, it is experimentally found that the inclusion of impedance networks of a silicon substrate, a package, and an evaluation board, is substantially effective to improve the accuracy of noise analysis. Quantitative correlation among simulation with on-chip noise measurements is demonstrated in a 90-nm 1.2-V CMOS technology.
ER -
English
