This paper discusses the impact of stacking on-chip inductor on power/ground network. Stacking inductor on other circuit components can reduce the circuit area drastically, however, the impact on signal and power integrity is not clear. We investigate the impact by a field-solver, a circuit simulator and real chip measurement. We evaluate three types of power/ground network and various multi-layered inductors. Experimental results show that dense power/ground structures reduce noise although the coupling capacitance becomes larger than that of sparse structures. Measurement in a 65-nm CMOS shows a woven structure makes the noise voltage half compared to a sparse structure.

An efficient reciprocity and passivity preserving balanced truncation for RLC networks is presented in this paper. Reciprocity and passivity are fundamental principles of linear passive networks. Hence, reduction with preservation of reciprocity and passivity is necessary to simulate behavior of the circuits including the RLC networks accurately and stably. Moreover, the proposed method is more efficient than the previous balanced truncation methods, because sparsity patterns of the coefficient matrices for the circuit equations of the RLC networks are fully available. In the illustrative examples, we will show that the proposed method is compatible with PRIMA, which is known as a general reduction method of RLC networks, in efficiency and used memory, and is more accurate at high frequencies than PRIMA.

An efficient balanced truncation for RC and RLC networks is presented in this paper. To accelerate the balanced truncation, sparse structures of original networks are considered. As a result, Lyapunov equations, the solutions of which are necessary for making the transformation matrices, are efficiently solved, and the reduced order models are efficiently obtained. It is proven that reciprocity of original networks is preserved while applying the proposed method. Passivity of the reduced RC networks is also guaranteed. In the illustrative examples, we will show that the proposed method is compatible with PRIMA in efficiency and is more accurate than PRIMA.

This paper proposes a power supply voltage control technique, and demonstrates its effectiveness for eliminating the overkills and underkills due to the power supply characteristic difference between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method controls the static power supply voltage on the ATE system, so that the ATE can eliminate misjudges for the Pass or Fail of the DUT. The method for calculating the power supply voltage is also described. Experimental results show that the proposed method can eliminate 89% of overkills and underkills in delay fault testing with 105 real silicon devices. Limitations of the proposed method are also discussed.

The alternating direction implicit (ADI) method is proposed for low-rank solution of projected generalized continuous-time algebraic Lyapunov equations. The low-rank solution is expressed by Cholesky factor that is similar to that of Cholesky factorization for linear system of equations. The Cholesky factor is represented in a real form so that it is useful for balanced truncation of sparsely connected RLC networks. Moreover, we show how to determine the shift parameters which are required for the ADI iterations, where Krylov subspace method is used for finding the shift parameters that reduce the residual error quickly. In the illustrative examples, we confirm that the real Cholesky factor certainly provides low-rank solution of projected generalized continuous-time algebraic Lyapunov equations. Effectiveness of the shift parameters determined by Krylov subspace method is also demonstrated.

This paper demonstrates the resonant power supply noise reduction effects of STO thin film decoupling capacitors, which are embedded in interposers. The on-interposer STO capacitor consists of SrTiO2 whose dielectric constant is about 20 and is sandwitched by Cu films in an interposer. The on-interposer STO capacitors are directly connected to the LSI PADs so that they provide large decoupling capacitance without package leadframe/bonding wire inductance, resulting in the reduction of the resonant power supply noise. The measured power supply waveforms show significant reduction of the power supply noise, and the Shmoo plots also show the contribution of the STO capacitors to the robust operations of LSIs.

Fast simulation techniques of large scale RLC networks with nonlinear devices are presented. Generally, when scale of nonlinear part in a circuit is much less than the linear part, matrix or circuit partitioning approach is known to be efficient. In this paper, these partitioning techniques are used for the conventional transient analysis using an implicit numerical integration and the circuit-based finite-difference time-domain (FDTD) method, whose efficiency and accuracy are evaluated developing a prototype simulator. It is confirmed that the matrix and circuit partitioning approaches do not degrade accuracy of the transient simulations that is compatible to SPICE, and that the circuit partitioning approach is superior to the matrix one in efficiency. Moreover, it is demonstrated that the circuit-based FDTD method can be efficiently combined with the matrix or circuit partitioning approach, compared with the transient analysis using an implicit numerical integration.

A three dimensional (3D) chip stack featuring a 4096-bit wide I/O demonstrator incorporates an in-place waveform capturer on an intermediate interposer within the stack. The capturer includes probing channels on paths of signaling as well as in power delivery and collects analog waveforms for diagnosing circuits within 3D integration. The collection of in-place waveforms on vertical channels with through silicon vias (TSVs) are demonstrated among 128 vertical I/O channels distributed in 8 banks in a 9.9mm × 9.9mm die area. The analog waveforms confirm a full 1.2-V swing of signaling at the maximum data transmission bandwidth of 100GByte/sec with sufficiently small deviations of signal skews and slews among the vertical channels. In addition, it is also experimentally confirmed that the signal swing can be reduced to 0.75V for error free data transfer at 100GByte/sec, achieving the energy efficiency of 0.21pJ/bit.

An LSI Chip-Package-Board integrated power noise simulation model and its validity is discussed in this paper. A unified power delivery network (PDN) of LSI chip, package, and printed circuit board (PCB) is connected with on-chip power supply current models with capacitor charging expression. The proposed modeling flow is demonstrated for the 32-bit microprocessor in a 1.0V 90nm CMOS technology. The PDN of the system that includes a chip, bonding wires and a printed circuit board is modeled in an equivalent circuit. The on-chip power supply noise monitoring technique and the magnetic probe method is applied for validating simulation results. Simulations and measurements explore power supply noise generation with the dependency on operating frequencies in the wide range from 10MHz to 300MHz, under the operation mode of dynamic frequency scaling, and in the long time operation with various operation codes. It is confirmed that the proposed power supply noise simulation model is helpful for the noise estimation throughout the design phase of the LSI system.

Substrate coupling of radio frequency (RF) components is represented by equivalent circuits unifying a resistive mesh network with lumped capacitors in connection with the backside of device models. Two-port S-parameter test structures are used to characterize the strength of substrate coupling of resistors, capacitors, inductors, and MOSFETs in a 65 nm CMOS technology with different geometries and dimensions. The consistency is finely demonstrated between simulation with the equivalent circuits and measurements of the test structures, with the deviation of typically less than 3 dB for passive and 6 dB for active components, in the transmission properties for the frequency range of interest up to 8 GHz.

An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.

Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100 Mbps. A pair of transceivers consumes 1.35 mA from 3.3 V, at 130 Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30 dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50 dB.

This paper presents generating stable and sparse reluctance/inductance matrix from the inductance matrix which is extracted under insufficient discretization. To generate the sparse reluctance matrix with guaranteed stability, the original matrix has to be (strictly) diagonally dominant M matrix. Hence, the repeated inductance extractions with a smaller grid size are necessary in order to obtain the well-defined matrix. Alternatively, this paper provides some ideas for generating the sparse reluctance matrix, even if the extracted reluctance matrix is not diagonally dominant M matrix. These ease the extraction tasks greatly. Furthermore, the sparse inductance matrix is also generated by using double inverse methods. Since reluctance components are not still supported in SPICE-like simulators, generating the sparse inductance matrix is more useful than the sparse reluctance one.

Capacitance charging modeling efficiently captures power supply currents in dynamic operations of a CMOS digital circuit and accurately expresses their interaction with on- and off-chip impedance networks. Derivation of such models is generally defined for combinational and sequential logic functions. Simulated substrate and power noises due to sequential logic operation show clear dependency on the size of circuits as well as the internal activity of logic gates. Furthermore, it is experimentally found that the inclusion of impedance networks of a silicon substrate, a package, and an evaluation board, is substantially effective to improve the accuracy of noise analysis. Quantitative correlation among simulation with on-chip noise measurements is demonstrated in a 90-nm 1.2-V CMOS technology.

In this paper, a novel method of partially placing electromagnetic band-gap (EBG) unit cells on both the power and ground planes in multi-layer PCBs and packages is proposed; it can not only sufficiently eliminate simultaneous switching noise (SSN), but also prevent severe degradation of signal quality in high-speed systems with imperfect reference planes resulting from the perforated structures of uni-planar EBG unit cells. On the assumption that the noise sources and noise-sensitive devices exist only in specific areas, the proposed method partially arranges the EBG unit cells on both the power and ground planes, but only around the critical areas. The SSN suppression performance of the proposed structure is verified by a simulation and measurements.

To build a stable power distribution network for high-speed digital systems, simultaneous switching noise (SSN) should be sufficiently suppressed in multi-layer PCBs and packages. In this paper, a novel hybrid uni-planar compact electromagnetic bandgap (UC-EBG) with two triangular-type unit cells designed on power/ground planes is proposed for the ultra-broadband suppression of SSN. The SSN suppression performance of the proposed structure is validated both numerically and experimentally. A -35 dB suppression bandwidth for SSN is achieved, starting at 800 MHz and extending to 15 GHz and beyond, thereby covering almost the entire noise band.

An on-chip power supply noise canceller with higher voltage supply and switching transistor is proposed and the effectiveness of the canceller is experimentally verified. The noise canceller is effective for nano-second order noise caused by circuit wakeup or step increase of frequency in frequency hopping. The principle of the noise canceller is to reduce the current flowing through the supply line of VDD by injecting additional current from the higher voltage supply, so that the voltage drop across the VDD supply line is reduced. As additional current flow from higher supply, switching transistor has to be turned off not to increase the power consumption. With turn-off time of 2L/R, this current can be turned off without inducting another droop due to the increase of current flowing through the power supply line. The measurement shows the canceller reduces 68% of the noise with load circuit equivalent to 530 k logic gates in 90-nm CMOS with 9% wire overhead, 1.5% area overhead, and 3% power overhead at 50 k wake-ups/s. Compared to passive noise reduction, proposed noise canceller reduces power supply noise by 64% without wire overhead and to achieve same noise reduction with passive method, 77 times more C or 45 times less L is required. Too large switching transistor results in saturated noise reduction effect and higher power consumption. A rule-of-thumb is to set the on-resistance to supply 100% of load current when turned-on.

This paper describes the modeling and the analysis methodology to evaluate Simultaneous Switching Noise (SSN) for the combined system of the package with the 4-layer Printed Circuit Board (PCB), which the 64 Simultaneous Switching Outputs (SSOs) were included using a simple IBIS model. Simulation results showed that the ground plane in both package and PCB can be used as the reference to reduce SSN more effectively than the power plane. For the source synchronous timing technique such as used in a DDR SDRAM memory bus in the model shown in this paper, the skew control circuit tequiniqe is easy to apply in the chip design instead of using embedded capacitors in the package's substrate. And also the radiated emission and eye diagram analysis were studied.

A fast time-domain simulation technique of plane circuits via two-layer Cellular Neural Network (CNN)-based modeling, which is necessary for power/signal integrity evaluation in VLSIs, printed circuit boards, and packages, is presented. Using the new notation expressed by the two-layer CNN, 1,553 times faster simulation is achieved, compared with Berkeley SPICE (ngspice). In CNN community, CNNs are generally simulated by explicit numerical integration such as the forward Euler and Runge-Kutta methods. However, since the two-layer CNN is a stiff circuit, we cannot analyze it by using an explicit numerical integration method. Hence, to analyze the two-layer CNN and reduce the computational cost, the leapfrog method is introduced. This procedure would open an application of CNN to electronic design automation area.

This paper presents a fast transient simulation method for power distribution networks (PDNs) of the PCB/Package. Because these PDNs are modeled as large-scale linear circuits consisting of a large number of RLC elements, it takes large costs to solve by conventional circuit simulators, such as SPICE. Our simulation method is based on the leapfrog algorithm, and can solve RLC circuits of PDNs faster than SPICE. Actual PDNs have frequency-dependent dispersions such as the skin-effect of conductors and the dielectric loss. To model these dispersions, more number of RLC elements are required, and circuit structures of these dispersion models are hard to solve by using the leapfrog algorithm. This paper shows that the circuit structures of dispersion models can be converted to suitable structures for the leapfrog algorithm. Further, in order to reduce the simulation time, our proposed method exploits parallel computation techniques. Numerical results show that our proposed method using single processing element (PE) enables a speedup of 20-100 times and 10 times compared to HSPICE and INDUCTWISE with the same level of accuracy, respectively. In a large-scale example with frequency-dependent dispersions, our method achieves over 94% parallel efficiency with 5PEs.