IEICE TRANSACTIONS on Electronics
AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model
Summary :
An LSI Chip-Package-Board integrated power noise simulation model and its validity is discussed in this paper. A unified power delivery network (PDN) of LSI chip, package, and printed circuit board (PCB) is connected with on-chip power supply current models with capacitor charging expression. The proposed modeling flow is demonstrated for the 32-bit microprocessor in a 1.0V 90nm CMOS technology. The PDN of the system that includes a chip, bonding wires and a printed circuit board is modeled in an equivalent circuit. The on-chip power supply noise monitoring technique and the magnetic probe method is applied for validating simulation results. Simulations and measurements explore power supply noise generation with the dependency on operating frequencies in the wide range from 10MHz to 300MHz, under the operation mode of dynamic frequency scaling, and in the long time operation with various operation codes. It is confirmed that the proposed power supply noise simulation model is helpful for the noise estimation throughout the design phase of the LSI system.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E97-C No.4 pp.264-271
- Publication Date
- 2014/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E97.C.264
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design,---,Architecture, Circuit, Device and Design Methodology)
- Category
Authors
Kumpei YOSHIKAWA
Kobe University
Kouji ICHIKAWA
DENSO CORPORATION
Makoto NAGATA
Kobe University
Keyword
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Kumpei YOSHIKAWA, Kouji ICHIKAWA, Makoto NAGATA, "AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model" in IEICE TRANSACTIONS on Electronics,
vol. E97-C, no. 4, pp. 264-271, April 2014, doi: 10.1587/transele.E97.C.264.
Abstract: An LSI Chip-Package-Board integrated power noise simulation model and its validity is discussed in this paper. A unified power delivery network (PDN) of LSI chip, package, and printed circuit board (PCB) is connected with on-chip power supply current models with capacitor charging expression. The proposed modeling flow is demonstrated for the 32-bit microprocessor in a 1.0V 90nm CMOS technology. The PDN of the system that includes a chip, bonding wires and a printed circuit board is modeled in an equivalent circuit. The on-chip power supply noise monitoring technique and the magnetic probe method is applied for validating simulation results. Simulations and measurements explore power supply noise generation with the dependency on operating frequencies in the wide range from 10MHz to 300MHz, under the operation mode of dynamic frequency scaling, and in the long time operation with various operation codes. It is confirmed that the proposed power supply noise simulation model is helpful for the noise estimation throughout the design phase of the LSI system.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E97.C.264/_p
Copy
@ARTICLE{e97-c_4_264,
author={Kumpei YOSHIKAWA, Kouji ICHIKAWA, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model},
year={2014},
volume={E97-C},
number={4},
pages={264-271},
abstract={An LSI Chip-Package-Board integrated power noise simulation model and its validity is discussed in this paper. A unified power delivery network (PDN) of LSI chip, package, and printed circuit board (PCB) is connected with on-chip power supply current models with capacitor charging expression. The proposed modeling flow is demonstrated for the 32-bit microprocessor in a 1.0V 90nm CMOS technology. The PDN of the system that includes a chip, bonding wires and a printed circuit board is modeled in an equivalent circuit. The on-chip power supply noise monitoring technique and the magnetic probe method is applied for validating simulation results. Simulations and measurements explore power supply noise generation with the dependency on operating frequencies in the wide range from 10MHz to 300MHz, under the operation mode of dynamic frequency scaling, and in the long time operation with various operation codes. It is confirmed that the proposed power supply noise simulation model is helpful for the noise estimation throughout the design phase of the LSI system.},
keywords={},
doi={10.1587/transele.E97.C.264},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model
T2 - IEICE TRANSACTIONS on Electronics
SP - 264
EP - 271
AU - Kumpei YOSHIKAWA
AU - Kouji ICHIKAWA
AU - Makoto NAGATA
PY - 2014
DO - 10.1587/transele.E97.C.264
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E97-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2014
AB - An LSI Chip-Package-Board integrated power noise simulation model and its validity is discussed in this paper. A unified power delivery network (PDN) of LSI chip, package, and printed circuit board (PCB) is connected with on-chip power supply current models with capacitor charging expression. The proposed modeling flow is demonstrated for the 32-bit microprocessor in a 1.0V 90nm CMOS technology. The PDN of the system that includes a chip, bonding wires and a printed circuit board is modeled in an equivalent circuit. The on-chip power supply noise monitoring technique and the magnetic probe method is applied for validating simulation results. Simulations and measurements explore power supply noise generation with the dependency on operating frequencies in the wide range from 10MHz to 300MHz, under the operation mode of dynamic frequency scaling, and in the long time operation with various operation codes. It is confirmed that the proposed power supply noise simulation model is helpful for the noise estimation throughout the design phase of the LSI system.
ER -
English
