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[Keyword] LSI chip-package-board co-design(2hit)

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  • AC Power Supply Noise Simulation of CMOS Microprocessor with LSI Chip-Package-Board Integrated Model

    Kumpei YOSHIKAWA  Kouji ICHIKAWA  Makoto NAGATA  

     
    PAPER

      Vol:
    E97-C No:4
      Page(s):
    264-271

    An LSI Chip-Package-Board integrated power noise simulation model and its validity is discussed in this paper. A unified power delivery network (PDN) of LSI chip, package, and printed circuit board (PCB) is connected with on-chip power supply current models with capacitor charging expression. The proposed modeling flow is demonstrated for the 32-bit microprocessor in a 1.0V 90nm CMOS technology. The PDN of the system that includes a chip, bonding wires and a printed circuit board is modeled in an equivalent circuit. The on-chip power supply noise monitoring technique and the magnetic probe method is applied for validating simulation results. Simulations and measurements explore power supply noise generation with the dependency on operating frequencies in the wide range from 10MHz to 300MHz, under the operation mode of dynamic frequency scaling, and in the long time operation with various operation codes. It is confirmed that the proposed power supply noise simulation model is helpful for the noise estimation throughout the design phase of the LSI system.

  • Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits

    Kumpei YOSHIKAWA  Yuta SASAKI  Kouji ICHIKAWA  Yoshiyuki SAITO  Makoto NAGATA  

     
    PAPER-Device and Circuit Modeling and Analysis

      Vol:
    E95-A No:12
      Page(s):
    2284-2291

    Capacitor charging modeling efficiently and accurately represents power consumption current of CMOS digital circuits and actualizes co-simulation of AC power noise including the interaction with on-chip and on-board integrated power delivery network (PDN). It is clearly demonstrated that the AC power noise is dominantly characterized by the frequency-dependent impedance of PDN and also by the operating frequency of circuits as well. A 65 nm CMOS chip exhibits the AC power noise components in substantial relation with the parallel resonance of the PDN seen from on-chip digital circuits. An on-chip noise monitor measures in-circuit power supply voltage, while a near-field magnetic probing derives on-board power supply current. The proposed co-simulation well matches the power noise measurements. The proposed AC noise co-simulation will be essentially applicable in the design of PDNs toward on-chip power supply integrity (PSI) and off-chip electromagnetic compatibility (EMC).