Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits
Summary :
Capacitor charging modeling efficiently and accurately represents power consumption current of CMOS digital circuits and actualizes co-simulation of AC power noise including the interaction with on-chip and on-board integrated power delivery network (PDN). It is clearly demonstrated that the AC power noise is dominantly characterized by the frequency-dependent impedance of PDN and also by the operating frequency of circuits as well. A 65 nm CMOS chip exhibits the AC power noise components in substantial relation with the parallel resonance of the PDN seen from on-chip digital circuits. An on-chip noise monitor measures in-circuit power supply voltage, while a near-field magnetic probing derives on-board power supply current. The proposed co-simulation well matches the power noise measurements. The proposed AC noise co-simulation will be essentially applicable in the design of PDNs toward on-chip power supply integrity (PSI) and off-chip electromagnetic compatibility (EMC).
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E95-A No.12 pp.2284-2291
- Publication Date
- 2012/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E95.A.2284
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Device and Circuit Modeling and Analysis
Authors
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Kumpei YOSHIKAWA, Yuta SASAKI, Kouji ICHIKAWA, Yoshiyuki SAITO, Makoto NAGATA, "Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E95-A, no. 12, pp. 2284-2291, December 2012, doi: 10.1587/transfun.E95.A.2284.
Abstract: Capacitor charging modeling efficiently and accurately represents power consumption current of CMOS digital circuits and actualizes co-simulation of AC power noise including the interaction with on-chip and on-board integrated power delivery network (PDN). It is clearly demonstrated that the AC power noise is dominantly characterized by the frequency-dependent impedance of PDN and also by the operating frequency of circuits as well. A 65 nm CMOS chip exhibits the AC power noise components in substantial relation with the parallel resonance of the PDN seen from on-chip digital circuits. An on-chip noise monitor measures in-circuit power supply voltage, while a near-field magnetic probing derives on-board power supply current. The proposed co-simulation well matches the power noise measurements. The proposed AC noise co-simulation will be essentially applicable in the design of PDNs toward on-chip power supply integrity (PSI) and off-chip electromagnetic compatibility (EMC).
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E95.A.2284/_p
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@ARTICLE{e95-a_12_2284,
author={Kumpei YOSHIKAWA, Yuta SASAKI, Kouji ICHIKAWA, Yoshiyuki SAITO, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits},
year={2012},
volume={E95-A},
number={12},
pages={2284-2291},
abstract={Capacitor charging modeling efficiently and accurately represents power consumption current of CMOS digital circuits and actualizes co-simulation of AC power noise including the interaction with on-chip and on-board integrated power delivery network (PDN). It is clearly demonstrated that the AC power noise is dominantly characterized by the frequency-dependent impedance of PDN and also by the operating frequency of circuits as well. A 65 nm CMOS chip exhibits the AC power noise components in substantial relation with the parallel resonance of the PDN seen from on-chip digital circuits. An on-chip noise monitor measures in-circuit power supply voltage, while a near-field magnetic probing derives on-board power supply current. The proposed co-simulation well matches the power noise measurements. The proposed AC noise co-simulation will be essentially applicable in the design of PDNs toward on-chip power supply integrity (PSI) and off-chip electromagnetic compatibility (EMC).},
keywords={},
doi={10.1587/transfun.E95.A.2284},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2284
EP - 2291
AU - Kumpei YOSHIKAWA
AU - Yuta SASAKI
AU - Kouji ICHIKAWA
AU - Yoshiyuki SAITO
AU - Makoto NAGATA
PY - 2012
DO - 10.1587/transfun.E95.A.2284
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E95-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2012
AB - Capacitor charging modeling efficiently and accurately represents power consumption current of CMOS digital circuits and actualizes co-simulation of AC power noise including the interaction with on-chip and on-board integrated power delivery network (PDN). It is clearly demonstrated that the AC power noise is dominantly characterized by the frequency-dependent impedance of PDN and also by the operating frequency of circuits as well. A 65 nm CMOS chip exhibits the AC power noise components in substantial relation with the parallel resonance of the PDN seen from on-chip digital circuits. An on-chip noise monitor measures in-circuit power supply voltage, while a near-field magnetic probing derives on-board power supply current. The proposed co-simulation well matches the power noise measurements. The proposed AC noise co-simulation will be essentially applicable in the design of PDNs toward on-chip power supply integrity (PSI) and off-chip electromagnetic compatibility (EMC).
ER -
English
