Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails
Summary :
Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100 Mbps. A pair of transceivers consumes 1.35 mA from 3.3 V, at 130 Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30 dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50 dB.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.6 pp.842-848
- Publication Date
- 2010/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.842
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
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Takushi HASHIDA, Makoto NAGATA, "Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 6, pp. 842-848, June 2010, doi: 10.1587/transele.E93.C.842.
Abstract: Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100 Mbps. A pair of transceivers consumes 1.35 mA from 3.3 V, at 130 Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30 dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50 dB.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.842/_p
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@ARTICLE{e93-c_6_842,
author={Takushi HASHIDA, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails},
year={2010},
volume={E93-C},
number={6},
pages={842-848},
abstract={Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100 Mbps. A pair of transceivers consumes 1.35 mA from 3.3 V, at 130 Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30 dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50 dB.},
keywords={},
doi={10.1587/transele.E93.C.842},
ISSN={1745-1353},
month={June},}
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TY - JOUR
TI - Chip-to-Chip Half Duplex Spiking Data Communication over Power Supply Rails
T2 - IEICE TRANSACTIONS on Electronics
SP - 842
EP - 848
AU - Takushi HASHIDA
AU - Makoto NAGATA
PY - 2010
DO - 10.1587/transele.E93.C.842
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2010
AB - Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100 Mbps. A pair of transceivers consumes 1.35 mA from 3.3 V, at 130 Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30 dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50 dB.
ER -
English
