Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100 Mbps. A pair of transceivers consumes 1.35 mA from 3.3 V, at 130 Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30 dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50 dB.

Testing is a critical stage in integrated circuits production in order to guarantee reliability. The complexity and high integration level of mixed-signal ICs has put forward new challenges to circuit testing. This paper describes an oscillation-based combined self-test strategy for the analog portion and analog-to-digital converters (ADCs) in integrated mixed-signal circuits. In test mode, the analog portion under test is reconfigured into an oscillator, generating periodic signals as the test stimulus of ADC. By analyzing the A/D conversion results, a histogram test of ADC can be performed, and the oscillation frequency as well as amplitude can be checked, and in this way the oscillation test of the analog portion is realized simultaneously. For an analog benchmark circuit combined with an ADC, triangle oscillation and sinusoid oscillation schemes are both given to test their faults. Experimental results show that fault coverage of the analog portion is 92.2% and 94.3% in the two schemes respectively, and faults in the ADC can also be tested.

Band connections employed in active cancellation circuits for effective reduction of digital substrate noise are proposed. An almost-odd-symmetrical noise characteristic is utilized for canceling out noises. Advancing this idea, interlaced connections of four bands are also proposed. Excess cancellation by those bands is more effective for noise reduction in a guard ring than a cancellation by two bands. Use of L-shaped bands on the basis of the interlaced connection suppresses the noise more. Simulation and experimental results show that the proposed band connections reduce the noise.

This paper proposes an operation-region model for analyzing and testing analog and mixed-signal circuits, which is based on observation of change in MOSFET operation regions. First, the relation between the change in MOSFET operation regions and the fault behavior of a mixed-signal circuit containing a bridging fault is investigated. Next, we propose an analysis procedure based on the operation-region model and apply it to generate the optimal input combination for testing the circuit. We also determine which transistors should be observed in order to estimate the circuit behavior. Since the operation-region model is a method for modeling circuit behavior abstractly, the proposed method will be useful for modeling circuit behavior and for analyzing and testing many kinds of analog and mixed-signal circuits.

The relationship between the change in transistor operation regions and the fault behavior of a mixed-signal circuit having a bridging fault was investigated. We also discussed determination of transistors to be observed for estimating the fault behavior. These results will be useful for modeling faulty behaviors and analyzing and diagnosing faults in mixed-signal circuits.

This paper deals with the problems in testing large mixed-signal ICs. To help generating test patterns of these larger mixed-signal circuits for a functional test, a fast fault simulation algorithm and a fault model voltage stuck-at fault" which the algorithm is based on, are proposed. A voltage stuck-at fault is that a signal line sticks its voltage level at a certain constant. Under an assumption that blocks in a circuit are designed as identically current-independent, i.e. their input impedance can be regarded as infinite and their output impedance as zero, fault simulation can be realized by the event driven method and the concurrent method and can detect voltage stuck-at faults. These methods are essential for digital fault simulation and very effective to high speed simulation, although they were impossible for an analog or mixed-signal circuit by a conventional algorithm. Furthermore, the efficiency of the simulation is improved because I/O relation of blocks is approximated to a stepwise linear function. The above techniques and methods make fault simulation for a mixed-signal circuit possible in practical use. Actually, a fault simulator was implemented, then some test circuits were simulated. The simulator is really faster than conventional simulation based on circuit simulation. Next, fault analysis was applied to several bipolar ICs to verify the validity of the fault model voltage stuck-at faults". Analyses of open and short faults between terminals of transistors and resistors show that this fault model has sufficient coverage (more than 50%) to test mixed-signal circuit.

Current testing has been proposed as an alternative technique for testing fully CMOS digital LSIs. Current testing has higher fault coverage than conventional stuck-at fault (SAF) testing and is more economical because it detects a wide range of faults and requires fewer test vectors than does SAF testing. We have proposed a current testing that measures the integral of the power supply current (IDD) during one clock period including the switching current. Since this method cannot be affected by the switching current, it can be used to test an LSI operating at a relatively high clock freuqnecy. This paper presents an improved current testing method for CMOS digital and analog LSIs. The method uses two current values (i.e., an upper limit and a lower limit) and judges the circuit under test to be faulty if the measured IDD is outside these limits. The proposed current testing is evaluated here for some kinds of faults (e.g., the bridging fault and the breaking fault) in digital and mixed-signal LSIs, and its efficiency of the current testing using SPICE3.