Hang Liu Fei Wu
Keiji GOTO Toru KAWANO Ryohei NAKAMURA
Takahiro SASAKI Yukihiro KAMIYA
Xiang XIONG Wen LI Xiaohua TAN Yusheng HU
Anton WIDARTA
Hiroshi OKADA Mao FUKINAKA Yoshiki AKIRA
Shun-ichiro Ohmi
Tohgo HOSODA Kazuyuki SAITO
Shohei Matsuhara Kazuyuki Saito Tomoyuki Tajima Aditya Rakhmadi Yoshiki Watanabe Nobuyoshi Takeshita
Koji Abe Mikiya Kuzutani Satoki Furuya Jose A. Piedra-Lorenzana Takeshi Hizawa Yasuhiko Ishikawa
Yihan ZHU Takashi OHSAWA
Shengbao YU Fanze MENG Yihan SHEN Yuzhu HAO Haigen ZHOU
Ryo KUMAGAI Ryosuke SUGA Tomoki UWANO
Jun SONODA Kazusa NAKAMICHI
Kaiji Owaki Yusuke Kanda Hideaki Kimura
Takuya FUJIMOTO
Yuji Wada
Fuyuki Kihara Chihiro Matsui Ken Takeuchi
Keito YUASA Michihiro IDE Sena KATO Kenichi OKADA Atsushi SHIRANE
Tomoo Ushio Yuuki Wada Syo Yoshida
Futoshi KUROKI
Jun FURUTA Shotaro SUGITANI Ryuichi NAKAJIMA Takafumi ITO Kazutoshi KOBAYASHI
Yuya Ichikawa Ayumu Yamada Naoko Misawa Chihiro Matsui Ken Takeuchi
Ayumu Yamada Zhiyuan Huang Naoko Misawa Chihiro Matsui Ken Takeuchi
Yoshinori ITOTAGAWA Koma ATSUMI Hikaru SEBE Daisuke KANEMOTO Tetsuya HIROSE
Hikaru SEBE Daisuke KANEMOTO Tetsuya HIROSE
Zhibo CAO Pengfei HAN Hongming LYU
Takuya SAKAMOTO Itsuki IWATA Toshiki MINAMI Takuya MATSUMOTO
Koji YAMANAKA Kazuhiro IYOMASA Takumi SUGITANI Eigo KUWATA Shintaro SHINJO
Minoru MIZUTANI Takashi OHIRA
Katsumi KAWAI Naoki SHINOHARA Tomohiko MITANI
Baku TAKAHARA Tomohiko MITANI Naoki SHINOHARA
Akihiko ISHIWATA Yasumasa NAKA Masaya TAMURA
Atsushi Fukuda Hiroto Yamamoto Junya Matsudaira Sumire Aoki Yasunori Suzuki
Ting DING Jiandong ZHU Jing YANG Xingmeng JIANG Chengcheng LIU
Fan Liu Zhewang Ma Masataka Ohira Dongchun Qiao Guosheng Pu Masaru Ichikawa
Ludovico MINATI
Minoru Fujishima
Hyunuk AHN Akito IGUCHI Keita MORIMOTO Yasuhide TSUJI
Kensei ITAYA Ryosuke OZAKI Tsuneki YAMASAKI
Akira KAWAHARA Jun SHIBAYAMA Kazuhiro FUJITA Junji YAMAUCHI Hisamatsu NAKANO
Seiya Kishimoto Ryoya Ogino Kenta Arase Shinichiro Ohnuki
Yasuo OHTERA
Tomohiro Kumaki Akihiko Hirata Tubasa Saijo Yuma Kawamoto Tadao Nagatsuma Osamu Kagaya
Haonan CHEN Akito IGUCHI Yasuhide TSUJI
Keiji GOTO Toru KAWANO Munetoshi IWAKIRI Tsubasa KAWAKAMI Kazuki NAKAZAWA
This paper discusses recent trends in the area of low-power, high-performance A/D conversion. We examine survey data collected over the past twelve years to show that the conversion energy of ADCs has halved every two years, while the speed-resolution product has doubled approximately only every four years. A closer inspection on the impact of technology scaling, and developments in ADC design are then presented to explain the observed trends. Finally, we review opportunities in digitally assisted design for the most popular converter architectures.
An operational amplifier is one of the key functional blocks and is widely used in analog and mixed-signal circuits. For low-power consumption, many techniques such as class AB and slew-rate enhancement have been proposed. Although phase compensation is related to power consumption, it has not been clearly discussed from the viewpoint of the power consumption. In this paper, the conventional and the improved Miller compensations and the phase compensation by introducing a new zero are dicussed for low-power operational amplifiers.
Shin'ichi ASAI Ken UENO Tetsuya ASAI Yoshihito AMEMIYA
We propose a CMOS circuit that can be used as an equivalent to resistors. This circuit uses a simple differential pair with diode-connected MOSFETs and operates as a high-resistance resistor when driven in the subthreshold region of MOSFETs. Its resistance can be controlled in a range of 1-1000 MΩ by adjusting a tail current for the differential pair. The results of device fabrication with a 0.35-µm 2P-4M CMOS process technology is described. The resistance was 13 MΩ for a tail current of 10 nA and 135 MΩ for 1 nA. The chip area was 105 µm
A low-voltage operational capability near 1 V along with low noise and distortion characteristics have been realized in a passive sigma-delta modulator. To achieve low-voltage operation, the dc voltage in signal paths in the switched-capacitor-filter section was set to be 0.2 V so that sufficient gate-to-source voltages were obtained for metal-oxide-semiconductor (MOS) switches in signal paths without using a gate-voltage boosting technique. In addition, the input switch that connects the input signal from the outside to the inside of an integrated circuit chip was replaced by a passive resistor to eliminate a floating switch, and gain coefficients in the feedback and input paths were modified so that the bias voltage of the digital-to-analog converter could be set to VDD and 0 V to easily activate MOS switches. As the signal swing becomes small under low-voltage operational circumstances, correlated double sampling was used to suppress the offset voltage and the 1/f noise that appeared at the input of a comparator. The modulator was fabricated using a standard CMOS 0.18-µm process, and the measured results show that the modulator realized 77 dB of dynamic range for 40 kHz of signal bandwidth with a 40 MHz sampling rate while dissipating 2 mW from a 1.1 V supply voltage.
Tuan Thanh TA Suguru KAMEDA Tadashi TAKAGI Kazuo TSUBOUCHI
In this paper, a fully integrated 5 GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18 µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1 GHz to 6.1 GHz (relative value of 17.9%) and phase noise of lower than -110.8 dBc/Hz at 1 MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182 dBc/Hz.
Shoichi HARA Kenichi OKADA Akira MATSUZAWA
This paper proposes a novel wideband voltage-controlled oscillator (VCO) for multi-band transceivers. The proposed oscillator has a core VCO and a tuning-range extension circuit, which consists of an injection-locked frequency divider (ILFD) and flip flop dividers. The two-stage differential ILFD generates quadrature outputs and realizes two, three, four, and six of divide ratio with very wide output frequency range. The proposed circuit is implemented by using a 90 nm CMOS process, and the chip area is 250
Chul NAM Joon-Sung PARK Young-Gun PU Kang-Yoon LEE
This paper presents a wide range DCO with fine discrete tuning steps using a ΣΔ modulation technique for UWB frequency synthesizer. The proposed discrete tuning scheme provides a low effective frequency resolution without any degradation of the phase noise performance. With its three step discrete tunings, the DCO simultaneously has a wide tuning range and fine tuning steps. The frequency synthesizer was implemented using 0.13 µm CMOS technology. The tuning range of the DCO is 5.8-6.8 GHz with an effective frequency resolution of 3.9 kHz. It achieves a measured phase noise of -108 dBc/Hz at 1 MHz offset and a tuning range of 16.8% with the power consumption of 5.9 mW. The figure of merit with the tuning range is -181.5 dBc/Hz.
Rui MURAKAMI Shoichi HARA Kenichi OKADA Akira MATSUZAWA
In this paper we present a study on the design optimization of voltage-controlled oscillators. The phase noise of LC-type oscillators is basically limited by the quality factor of inductors. It has been experimentally shown that higher-Q inductors can be achieved at higher frequencies while the oscillation frequency is limited by parasitic capacitances. In this paper, the minimum transistor size and the degradation of the quality factor caused by a switched-capacitor array are analytically estimated, and the maximum oscillation frequency of VCOs is also derived from an equivalent circuit by considering parasitic capacitances. According to the analytical evaluation, the phase noise of a VCO using a 65 nm CMOS is 2 dB better than that of a 180 nm CMOS.
Sung-Jin KIM Minchang CHO SeongHwan CHO
In this paper, an ultra low power analog front-end for EPCglobal Class 1 Generation 2 RFID tag is presented. The proposed RFID tag removes the need for high frequency clock and counters used in conventional tags, which are the most power hungry blocks. The proposed clock-free decoder employs an analog integrator with an adaptive current source that provides a uniform decoding margin regardless of the data rate and a link frequency extractor based on a relaxation oscillator that generates frequency used for backscattering. A dual supply voltage scheme is also employed to increase the power efficiency of the tag. In order to improve the tolerance of the proposed circuit to environmental variations, a self-calibration circuit is proposed. The proposed RFID analog front-end circuit is designed and simulated in 0.25 µm CMOS, which shows that the power consumption is reduced by an order magnitude compared to the conventional RFID tags, without losing immunity to environmental variations.
Lechang LIU Zhiwei ZHOU Takayasu SAKURAI Makoto TAKAMIYA
A low power impulse radio ultra-wideband (IR-UWB) receiver for DC-960 MHz band is proposed in this paper. The proposed receiver employs multiple DC power-free charge-domain sampling correlators to eliminate the need for phase synchronization. To alleviate BER degradation due to an increased charge injection in a subtraction operation in the sampling correlator than that of an addition operation, a comparator with variable threshold (=offset) voltage is used, which enables an addition-only operation. The developed receiver fabricated in 1.2 V 65 nm CMOS achieves the lowest energy consumption of 17.6 pJ/bit at 100 Mbps in state-of-the-art correlation-based UWB receivers.
Kenichi AGAWA Shinichiro ISHIZUKA Hideaki MAJIMA Hiroyuki KOBAYASHI Masayuki KOIZUMI Takeshi NAGANO Makoto ARAI Yutaka SHIMIZU Asuka MAKI Go URAKAWA Tadashi TERADA Nobuyuki ITOH Mototsugu HAMADA Fumie FUJII Tadamasa KATO Sadayuki YOSHITOMI Nobuaki OTSUKA
A 2.4 GHz 0.13 µm CMOS transceiver LSI, supporting Bluetooth V2.1+enhanced data rate (EDR) standard, has achieved a high reception sensitivity and high-quality transmission signals between -40
Naoki TAKAYAMA Kota MATSUSHITA Shogo ITO Ning LI Keigo BUNSEN Kenichi OKADA Akira MATSUZAWA
This paper proposes a de-embedding method for on-chip S-parameter measurements at mm-wave frequency. The proposed method uses only two transmission lines with different length. In the proposed method, a parasitic-component model extracted from two transmission lines can be used for de-embedding for other-type DUTs like transistor, capacitor, inductor, etc. The experimental results show that the error in characteristic impedance between the different-length transmission lines is less than 0.7% above 40 GHz. The extracted pad model is also shown.
Tetsuro MATSUNO Daisuke FUJIMOTO Daisuke KOSAKA Naoyuki HAMANISHI Ken TANABE Masazumi SHIOCHI Makoto NAGATA
An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.
Yuji OKAZAKI Takanori UNO Hideki ASAI
In this paper, we propose an optimization system with parallel processing for reducing electromagnetic interference (EMI) on electronic control unit (ECU). We adopt simulated annealing (SA), genetic algorithm (GA) and taboo search (TS) to seek optimal solutions, and a Spice-like circuit simulator to analyze common-mode current. Therefore, the proposed system can determine the adequate combinations of the parasitic inductance and capacitance values on printed circuit board (PCB) efficiently and practically, to reduce EMI caused by the common-mode current. Finally, we apply the proposed system to an example circuit to verify the validity and efficiency of the system.
Yusuke TSUGITA Ken UENO Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA
An on-chip process, supply voltage, and temperature (PVT) compensation technique for low-voltage CMOS digital circuits was proposed. Because the degradation of circuit performance originates from the variation of the saturation current in transistors, we developed a compensation circuit consisting of a reference current that is independent of PVT variations. The circuit is operated so that the saturation current in digital circuits is equal to the reference current. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-µm standard CMOS parameters. Monte Carlo simulations showed that the proposed technique effectively improves circuit performance by 71%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.
Chip-to-chip serial data communication is superposed on power supply over common Vdd/Vss connections through chip, package, and board traces. A power line transceiver demonstrates half duplex spiking communication at more than 100 Mbps. A pair of transceivers consumes 1.35 mA from 3.3 V, at 130 Mbps. On-chip power line LC low pass filter attenuates pseudo-differential communication spikes by 30 dB, purifying power supply current for internal circuits. Bi-directional spiking communication was successfully examined in a 90-nm CMOS prototype setup of on-chip waveform capturing. A micro controller forwards clock pulses to and receives data streams from a comparator based waveform capturer formed on a different chip, through a single pair of power and ground traces. The bit error rate is small enough not to degrade waveform acquisition capability, maintaining the spurious free dynamic range of higher than 50 dB.
Takeshi YOSHIDA Yoshihiro MASUI Ryoji EKI Atsushi IWATA Masayuki YOSHIDA Kazumasa UEMATSU
To detect neural spike signals, low-power neural signal recording frontend circuits must amplify neural signals with below 100 µV amplitude and a few hundred Hz frequency while suppressing a large DC offset voltage, 1/f noise of MOSFETs, and induced noise of AC power supply. To overcome the problem of unwanted noise at such a low signal level, a low-noise neural signal detection amplifier with low-frequency noise suppression scheme was developed utilizing a new autozeroing technique. A test chip was designed and fabricated with a mixed signal 0.18-µm CMOS technology. The voltage gain of 39 dB at the bandwidth of the neural signal and the gain reduction of 20 dB at AC supply noise of 60 Hz were obtained. The input equivalent noise and power dissipation were 90 nV/root-Hz and 90 µW at a supply voltage of 1.5 V, respectively.
A new fast-lock, low-power digital delay-locked loop (DLL) is presented. A subranging searching algorithm is employed to effectively make the loop locked within only four clock cycles. A half-delay circuit is utilized to cut down power consumption. The prototype DLL in a standard 0.13-µm CMOS process operates in the range from 50 MHz to 400 MHz with four clock cycle lock time and consumes 2.379 mW with 1-V supply at 400 MHz clock rate. The measured RMS jitter and peak-to-peak jitter at 400 MHz are 1.586 ps and 16.67 ps, respectively. It occupies an active area of 0.038 mm2.
A swing level controlled voltage-mode transmitter is proposed to support a stub series-terminated logic channel with center-tapped termination. This transmitter provides a swing level control to support the diagnostic mode and improve the signal integrity in the absence of the destination termination. By using the variable parallel termination, the proposed transmitter maintains the constant output impedance of the source termination while the swing level is controlled. Also, the series termination using an external resistor is used to reduce the impedance mismatch effect due to the parasitic components of the capacitor and inductor. To verify the proposed transmitter, the voltage-mode driver, which provides eight swing levels with the constant output impedance of about 50 Ω, was implemented using a 70 nm 1-poly 3-metal DRAM process with a 1.5 V supply. The jitter reduction of 54% was measured with the swing level controlled voltage-mode driver in the absence of the destination termination at 1.6-Gb/s.
Kozue SASAKI Hiroki SATO Akira HYOGO Keitaro SEKINE
This paper presents a CMOS signal detection circuit for 2.5 Gb/s serial data communication system over FR-4 backplane. This overcomes characteristics deviation of full-wave rectifier-based simple power detection circuits due to data pattern and temperature by using an edge detector and a sample-hold circuit.
Somboon THEERAWISITPONG Toshitatsu SUZUKI Noboru MORITA Yozo UTSUMI
The design of microstrip bandpass filters using stepped-impedance resonators (SIRs) is examined. The passband center frequency for the WCDMA-FDD (uplink band) Japanese cellular system is 1950 MHz with a 60-MHz bandwidth. The SIR physical characteristic can be designed using a SIR characteristic chart based on second harmonic suppression. In our filter design, passband design charts were obtained through the design procedure. Tchebycheff and maximally flat bandpass filters of any bandwidth and any number of steps can be designed using these passband design charts. In addition, sharp skirt characteristics in the passband can be realized by having two transmission zeros at both adjacent frequency bands by using open-ended quarter-wavelength stubs at input and output ports. A new even-mode harmonics suppression technique is proposed to enable a wide rejection band having a high suppression level. The unloaded quality factor of the resonator used in the proposed filters is greater than 240.
Po-Hung CHEN Min-Chiao CHEN Chun-Lin KO Chung-Yu WU
A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SFT) for V-band applications is designed, fabricated and measured using 0.13-µm CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SFT. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20 GHz. The fabricated receiver has a maximum conversion gain of 19.4 dB, a minimum single-side band noise figure of 10.2 dB, the input-referred 1-dB compression point of -20 dBm and the input third order inter-modulation intercept point of -8.3 dB. It draws only 15.8 mA from a 1.2-V power supply with a total chip area of 0.794 mm
Yoshio NISHIDA Koichi HAMASHITA Gabor C. TEMES
This paper presents an enhanced dual-path delta-sigma analog-to-digital converter. Compared with other architectures, the enhanced architecture increases the noise shaping order without any instability problems and displays analog complexity equivalent to the multi-stage noise shaping architecture. Our delta-sigma converter is based on this new architecture. It employs not only doubly-differential structure to reduce common-mode errors in the system-level but also delayed-feed-in structure to mitigate the timing constraint of the feedback signal. Regarding the circuit implementation, the first-order enhancement of the quantization noise shaping is achieved via the use of a switched capacitor circuit technique. The circuit is incorporated into the active adder in a low-distortion structure. The supporting clock generation circuit that provides additional phases of clocks with the enhancement block is also implemented in the CMOS logic gates. A digital dynamic element matching circuit (i.e., segmented data-weighted-average circuit) is designed to reduce mismatch errors caused by the feedback DAC of modulator. A test chip, fabricated in a 0.18-µm CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75-dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2nd harmonic is -101 dB and the 3rd harmonic is -94 dB when a -4.5-dB 100-kHz input signal is applied.
Jin SUN Kiran POTLURI Janet M. WANG
With the scaling down of CMOS devices, process variation is becoming the leading cause of CMOS based analog circuit failures. For example, a mere 5% variation in feature size can trigger circuit failure. Various methods such as Monte-Carlo and corner-based verification help predict variation caused problems at the expense of thousands of simulations before capturing the problem. This paper presents a new methodology for analog circuit performance prediction. The new method first applies statistical uncertainty analysis on all associated devices in the circuit. By evaluating the uncertainty importance of parameter variability, it approximates the circuit with only components that are most critical to output results. Applying Chebyshev Affine Arithmetic (CAA) on the resulting system provides both performance bounds and probability information in time domain and frequency domain.
Shigeru SAWADA Terutaka TAMAI Yasuhiro HATTORI Kazuo IIDA
Constriction resistance is calculated by numerical analysis using Laplace's equations for electric potential of steady state in many cases of contact spot dispersion-status. The results show that contact resistance does not increase beyond 1.5 times even if the total real contact area is about 15% of the apparent contact area. When real contact area is at least about 60% of the apparent contact area, the contact resistance is approximately the same as the constriction resistance acquired from the apparent contact area. When the real contact area is about 50% of the apparent contact area, the contact resistance is approximately constant without regard to the contact shape and contact-point dispersion layout. Therefore, it is proved that contact resistance can be practically calculated using apparent contact area instead of real contact area when there are many contact points caused by metal to metal contact.
Jisu KIM Jee-Hwan SONG Seung-Hyuk KANG Sei-Seung YOON Seong-Ook JUNG
Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising technology for next generation nonvolatile universal memory because it reduces the high write current required by conventional MRAM and enables write current scaling as technology becomes smaller in size. However, the sensing margin is not improved in STT-MRAM and tends to decrease with technology scaling due to the lowered supply voltage and increased process variation. Moreover, read disturbance, which is an unwanted write in a read operation, can occur in STT-MRAM because its read and write operations use the same path. To overcome these problems, we present a load-line analysis method, which is useful for systematically analyzing the impacts of transistor size and gate voltage of MOSFETs on the sensing margin, and also propose an optimization procedure for the commonly applicable MRAM sensing circuits. This methodology constitutes an effective means to optimize the transistor size and gate voltage of MOSFETs and thus maximizes the sensing margin without causing read disturbance.
Young-Bok JOO Chan-Ho HAN Kil-Houm PARK
LCD Automatic Vision Inspection (AVI) systems automatically detect defect features and measure their sizes via camera vision. AVI systems usually report different measurements on the same defect with some variations on position or rotation mainly because we get different images. This is caused by possible variations in the image acquisition process including optical factors, non-uniform illumination, random noise, and so on. For this reason, conventional area based defect measuring method has some problems in terms of robustness and consistency. In this paper, we propose a new defect size measuring method to overcome these problems. We utilize volume information which is completely ignored in the area based conventional defect measuring method. We choose a bell shape as a defect model for experiment. The results show that our proposed method dramatically improves robustness of defect size measurement. Given proper modeling, the proposed volume based measuring method can be applied to various types of defect for better robustness and consistency.
Yeong-Chul CHUNG Kyung-Won LEE Ic-Pyo HONG Kyung-Hyun OH Jong-Gwan YOOK
In this letter, a new CCM material, adding Ni powder to a conventional CCM, for X-band applications is designed and analyzed to improve the SE. To obtain the SE of the fabricated CCM accurately, material constants of the CCM of the permittivity and permeability were extracted using transmission/reflection measurements. Using the material constants derived from the measurement, the SE was calculated and the results were verified using a commercial full-wave three-dimensional electromagnetic wave simulator. The SE of the proposed the CCM was improved by approximately 4 dB in the X band compared to that of a conventional CCM. The CCM proposed in this paper can be applied as a shielding material as well as for housing of various communication systems and electrical instruments.
Keivan NAVI Fazel SHARIFI Amir MOMENI Peiman KESHAVARZIAN
In this paper an ultra high speed CNFET Full-Adder cell is presented. This design generates sum and carry-out signals via majority and majority-not gates which are implemented by CNFET buffer, CNFET inverter and input capacitors. Significant improvement in terms of speed and Power-Delay Product (PDP) is achieved.
Yeong-Shin JANG Hoai-Nam NGUYEN Seung-Tak RYU Sang-Gug LEE
An accurate behavioral model of a DAC-embedded opamp (DAC-opamp) is developed for a yield-ensuring LCD column driver design. A lookup table for the V-I curve of the unit differential pair in the DAC-opamp is extracted from a circuit simulation and is later manipulated through a random error insertion. Virtual ground assumption simplifies the output voltage estimation algorithm. The developed behavioral model of a 5-bit DAC-opamp shows good agreement with the circuit level simulation with less than 5% INL difference.