Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits

Jisu KIM; Jee-Hwan SONG; Seung-Hyuk KANG; Sei-Seung YOON; Seong-Ook JUNG

doi:10.1587/transele.E93.C.912

Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits

Jisu KIM, Jee-Hwan SONG, Seung-Hyuk KANG, Sei-Seung YOON, Seong-Ook JUNG

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Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising technology for next generation nonvolatile universal memory because it reduces the high write current required by conventional MRAM and enables write current scaling as technology becomes smaller in size. However, the sensing margin is not improved in STT-MRAM and tends to decrease with technology scaling due to the lowered supply voltage and increased process variation. Moreover, read disturbance, which is an unwanted write in a read operation, can occur in STT-MRAM because its read and write operations use the same path. To overcome these problems, we present a load-line analysis method, which is useful for systematically analyzing the impacts of transistor size and gate voltage of MOSFETs on the sensing margin, and also propose an optimization procedure for the commonly applicable MRAM sensing circuits. This methodology constitutes an effective means to optimize the transistor size and gate voltage of MOSFETs and thus maximizes the sensing margin without causing read disturbance.

Publication: IEICE TRANSACTIONS on Electronics Vol.E93-C No.6 pp.912-921

Publication Date: 2010/06/01

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Online ISSN: 1745-1353

DOI: 10.1587/transele.E93.C.912

Type of Manuscript: PAPER

Category: Integrated Electronics

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Jisu KIM, Jee-Hwan SONG, Seung-Hyuk KANG, Sei-Seung YOON, Seong-Ook JUNG, "Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits" in IEICE TRANSACTIONS on Electronics, vol. E93-C, no. 6, pp. 912-921, June 2010, doi: 10.1587/transele.E93.C.912.
Abstract: Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising technology for next generation nonvolatile universal memory because it reduces the high write current required by conventional MRAM and enables write current scaling as technology becomes smaller in size. However, the sensing margin is not improved in STT-MRAM and tends to decrease with technology scaling due to the lowered supply voltage and increased process variation. Moreover, read disturbance, which is an unwanted write in a read operation, can occur in STT-MRAM because its read and write operations use the same path. To overcome these problems, we present a load-line analysis method, which is useful for systematically analyzing the impacts of transistor size and gate voltage of MOSFETs on the sensing margin, and also propose an optimization procedure for the commonly applicable MRAM sensing circuits. This methodology constitutes an effective means to optimize the transistor size and gate voltage of MOSFETs and thus maximizes the sensing margin without causing read disturbance.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.912/_p

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@ARTICLE{e93-c_6_912,
author={Jisu KIM, Jee-Hwan SONG, Seung-Hyuk KANG, Sei-Seung YOON, Seong-Ook JUNG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits},
year={2010},
volume={E93-C},
number={6},
pages={912-921},
abstract={Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising technology for next generation nonvolatile universal memory because it reduces the high write current required by conventional MRAM and enables write current scaling as technology becomes smaller in size. However, the sensing margin is not improved in STT-MRAM and tends to decrease with technology scaling due to the lowered supply voltage and increased process variation. Moreover, read disturbance, which is an unwanted write in a read operation, can occur in STT-MRAM because its read and write operations use the same path. To overcome these problems, we present a load-line analysis method, which is useful for systematically analyzing the impacts of transistor size and gate voltage of MOSFETs on the sensing margin, and also propose an optimization procedure for the commonly applicable MRAM sensing circuits. This methodology constitutes an effective means to optimize the transistor size and gate voltage of MOSFETs and thus maximizes the sensing margin without causing read disturbance.},
keywords={},
doi={10.1587/transele.E93.C.912},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 912
EP - 921
AU - Jisu KIM
AU - Jee-Hwan SONG
AU - Seung-Hyuk KANG
AU - Sei-Seung YOON
AU - Seong-Ook JUNG
PY - 2010
DO - 10.1587/transele.E93.C.912
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2010
AB - Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising technology for next generation nonvolatile universal memory because it reduces the high write current required by conventional MRAM and enables write current scaling as technology becomes smaller in size. However, the sensing margin is not improved in STT-MRAM and tends to decrease with technology scaling due to the lowered supply voltage and increased process variation. Moreover, read disturbance, which is an unwanted write in a read operation, can occur in STT-MRAM because its read and write operations use the same path. To overcome these problems, we present a load-line analysis method, which is useful for systematically analyzing the impacts of transistor size and gate voltage of MOSFETs on the sensing margin, and also propose an optimization procedure for the commonly applicable MRAM sensing circuits. This methodology constitutes an effective means to optimize the transistor size and gate voltage of MOSFETs and thus maximizes the sensing margin without causing read disturbance.
ER -