This paper proposes a new biquad structure based on a flipped voltage follower (FVF) for low-power and wide-bandwidth (BW) low pass filter. The proposed biquad structure consists of an FVF and a source follower (SF) for complex pole pair generation and zero cancellation. The presented design provides good linearity at low power consumption, owing to the voltage follower structures. A power/BW ratio (PBWR) is suggested as a performance metric to compare power efficiency to bandwidth, and the proposed biquad structure shows excellent PBWR, especially for low quality factor (Q) design. As a prototype, a fourth order Bessel filter was fabricated in 0.18 µm CMOS technology. The measured BW, power consumption, IIP3, and FoM are 120 MHz, 180 µW, 15 dBm, and 0.34 fJ, respectively.

An accurate behavioral model of a DAC-embedded opamp (DAC-opamp) is developed for a yield-ensuring LCD column driver design. A lookup table for the V-I curve of the unit differential pair in the DAC-opamp is extracted from a circuit simulation and is later manipulated through a random error insertion. Virtual ground assumption simplifies the output voltage estimation algorithm. The developed behavioral model of a 5-bit DAC-opamp shows good agreement with the circuit level simulation with less than 5% INL difference.

A 20 kHz audio-band ADC with a single pair of power and ground pads is implemented for a digital electret microphone. Under the limited power/ground pad condition, the switching noise effect on the signal quality is estimated via post simulations with parasitic models. Performance degradation is minimized by time-domain noise isolation with sufficient time-spacing between the sampling edge and the output transition. The prototype ADC was implemented in a 0.18 µm CMOS process. It operates under a minimum supply voltage of 1.6 V with total current of 420 µA. Operating at 2.56 MHz clock frequency, it achieves 84 dB dynamic range and a 64 dB peak signal-to-(noise+distortion) ratio. The measured power supply rejection at a 100 mVpp 217 Hz square wave is -72 dB.

An on-chip CMOS preamplifier for direct signal readout from an electret capacitor microphone has been designed with high immunity to common-mode and supply noise. The Gm-Opamp-RC based high impedance preamplifier helps to remove all disadvantages of the conventional JFET based amplifier and can drive a following switched-capacitor sigma-delta modulator in order to realize a compact digital electret microphone. The proposed chip is designed based on 0.18 µm CMOS technology, and the simulation results show 86 dB of dynamic range with 4.5 µVrms of input-referred noise for an audio bandwidth of 20 kHz and a total harmonic distortion (THD) of 1% at 90 mVrms input. Power supply rejection ratio (PSRR) and common-mode rejection ration (CMRR) are more than 95 dB at 1 kHz. The proposed design dissipates 125 µA and can operate over a wide supply voltage range of 1.6 V to 3.3 V.