At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (Dgd) has been enlarged to obtain a better maximum available gain (MAG). By using the asymmetric-layout transistor, a 0.6 dB MAG improvement is realized when Dgd changes from 60 nm to 200 nm. A four-stage common-source low noise amplifier is implemented in a 65 nm CMOS process. A measured peak power gain of 24 dB is achieved with a power dissipation of 30 mW from a 1.2-V power supply. An 18 dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17 GHz from 51 GHz to 68 GHz, and noise figure (NF) is from 4.0 dB to 7.6 dB.

This paper proposes a de-embedding method for on-chip S-parameter measurements at mm-wave frequency. The proposed method uses only two transmission lines with different length. In the proposed method, a parasitic-component model extracted from two transmission lines can be used for de-embedding for other-type DUTs like transistor, capacitor, inductor, etc. The experimental results show that the error in characteristic impedance between the different-length transmission lines is less than 0.7% above 40 GHz. The extracted pad model is also shown.