We developed a 300-GHz high gain amplifier MMIC in 75-nm InP high electron mobility transistor technology. We approached the issues with accurate characterization of devices to design the amplifier. The on-wafer through-reflect-line calibration technique was used to obtain accurate transistor characteristics. To increase measurement accuracy, a highly isolated structure was used for on-wafer calibration standards. The common source amplifier topology was used for achieving high gain amplification. The implemented amplifier MMIC exhibited a gain of over 25 dB in the 280-310-GHz frequency band.

A wide-bandwidth fundamental mixer operating at a frequency above 110GHz for precise spectrum analysis was developed using the InP HEMT technology. A single-ended resistive mixer was adopted for the mixer circuit. An IF amplifier and LO buffer amplifier were also developed and integrated into the mixer chip. As for packaging into a metal block module, a flip-chip bonding technique was introduced. Compared to face-up mounting with wire connections, flip-chip bonding exhibited good frequency flatness in signal loss. The mixer module with a built-in IF amplifier achieved a conversion gain of 5dB at an RF frequency of 135GHz and a 3-dB bandwidth of 35GHz. The mixer module with an LO buffer amplifier operated well even at an LO power of -20dBm.

Floating-point units (FPUs) are indispensable in processors, 3D-graphic engines, etc. To improve design productivity of these LSIs, FPU IPs are strongly desired. However, it is impossible to cover wide range of needs by an FPU IP, because there are various kind of options in specifications (e.g., operating frequency, latency, and ability of pipeline operation) and implementations (e.g., hardware algorithms). Thus, multiple IPs are needed even for the same functionality. In this paper, we propose to build an IP Library which consists of large number of FPU IPs with various kind of specifications and implementations, and which has catalogue data that shows not only specifications but also post-layout area and power dissipation of each IP. As the first step of the project, we have developed an IP Library targeted to Rohm 0.35 µm triple-metal process, which consists of 20 IPs for IEEE-754-standard single-precision floating-point division with 5 operating frequencies (50 MHz, 75 MHz, 100 MHz, 125 MHz, and 150 MHz), with two options whether pipelined or not, and with two hardware algorithms (the restoring method and the SRT method). We have also developed a catalogue for the IP Library, which shows post-layout area and power dissipation as well as specification of each IP. We have introduced two metrics "performance-area ratio (MFLOPS/mm2)" and "performance-power ratio (MFLOPS/W)" to afford a good insight into efficiency of implementations. From the catalogue data, the restoring method is, on the average, 1.4 times and 2.3 times better than the SRT method in terms of performance-area ratio and performance-power ratio, respectively. The developed catalogue is usable not only for selection of the optimal IP for a specific application, but also for quantitative analysis at the early stage of architecture design. It is also expected that the catalogue data based on an actual process technology is valuable for education.

We report on robust and low-power-consumption InP- and GaN-HEMT Low-Noise-Amplifiers (LNAs) operating in Q-band frequency range. A multi-stage common-gate (CG) amplifier with current reuse topology was used. To improve the survivability of the CG amplifier, we introduced a feedback resistor at the gate bias feed. The design technique was adapted to InP- and GaN-HEMT LNAs. The 75nm gate length InP HEMT LNA exhibited a gain of 18dB and a noise figure (NF) of 3dB from 33 to 50GHz. The DC power consumption was 16mW. The Robustness of the InP HEMT LNA was tested by injecting a millimeter-wave input power of 13dBm for 10 minutes. No degradation in a small signal gain was observed. The fabricated 0.12µm gate length GaN HEMT LNA exhibited a gain of 15dB and an NF of 3.2dB from 35 to 42GHz. The DC power consumption was 280mW. The LNA survived until an input power of 28dBm.

At mm-wave frequency, the layout of CMOS transistors has a larger effect on the device performance than ever before in low frequency. In this work, the distance between the gate and drain contact (Dgd) has been enlarged to obtain a better maximum available gain (MAG). By using the asymmetric-layout transistor, a 0.6 dB MAG improvement is realized when Dgd changes from 60 nm to 200 nm. A four-stage common-source low noise amplifier is implemented in a 65 nm CMOS process. A measured peak power gain of 24 dB is achieved with a power dissipation of 30 mW from a 1.2-V power supply. An 18 dB variable gain is also realized by adjusting the bias voltage. The measured 3-dB bandwidth is about 17 GHz from 51 GHz to 68 GHz, and noise figure (NF) is from 4.0 dB to 7.6 dB.