Floating-point units (FPUs) are indispensable in processors, 3D-graphic engines, etc. To improve design productivity of these LSIs, FPU IPs are strongly desired. However, it is impossible to cover wide range of needs by an FPU IP, because there are various kind of options in specifications (e.g., operating frequency, latency, and ability of pipeline operation) and implementations (e.g., hardware algorithms). Thus, multiple IPs are needed even for the same functionality. In this paper, we propose to build an IP Library which consists of large number of FPU IPs with various kind of specifications and implementations, and which has catalogue data that shows not only specifications but also post-layout area and power dissipation of each IP. As the first step of the project, we have developed an IP Library targeted to Rohm 0.35 µm triple-metal process, which consists of 20 IPs for IEEE-754-standard single-precision floating-point division with 5 operating frequencies (50 MHz, 75 MHz, 100 MHz, 125 MHz, and 150 MHz), with two options whether pipelined or not, and with two hardware algorithms (the restoring method and the SRT method). We have also developed a catalogue for the IP Library, which shows post-layout area and power dissipation as well as specification of each IP. We have introduced two metrics "performance-area ratio (MFLOPS/mm2)" and "performance-power ratio (MFLOPS/W)" to afford a good insight into efficiency of implementations. From the catalogue data, the restoring method is, on the average, 1.4 times and 2.3 times better than the SRT method in terms of performance-area ratio and performance-power ratio, respectively. The developed catalogue is usable not only for selection of the optimal IP for a specific application, but also for quantitative analysis at the early stage of architecture design. It is also expected that the catalogue data based on an actual process technology is valuable for education.