The noise performance of common source and cascode topology 60 GHz LNAs is analyzed and verified. The analysis result shows that the noise performance of the cascode topology is degraded at high frequency due to the inter-stage node capacitance. The analysis result is verified by experimental results. A three-stage LNA employing two noise-matched CS stages and a cascode stage is proposed. For comparison a conventional two-stage cascode LNA is also been studied with the measurement-based model. The measured results of the proposed LNA show that an input and output matching of less than -10 dB, a maximum gain of 9.7 dB and a noise figure (NF) of 3.2 dB are obtained with a power consumption of 30 mW from a 1.2-V supply voltage. Compared to the conventional cascode LNA, an improvement of 2.3-dB for NF and 1.9-dB for power gain are realized. Both the proposed and conventional LNAs are implemented in 65 nm CMOS process.

This paper proposes a de-embedding method for on-chip S-parameter measurements at mm-wave frequency. The proposed method uses only two transmission lines with different length. In the proposed method, a parasitic-component model extracted from two transmission lines can be used for de-embedding for other-type DUTs like transistor, capacitor, inductor, etc. The experimental results show that the error in characteristic impedance between the different-length transmission lines is less than 0.7% above 40 GHz. The extracted pad model is also shown.

An L-2L through-line de-embedding method has been verified up to millimeter wave frequency. The parasitics of the pad can be modeled from the L-2L through-line. Measurement results of the transmission lines and transistors can be de-embedded by subtracting the parasitic matrix of the pad. Therefore, the de-embedding patterns, which is used for modeling active and passive devices, decrease greatly and the chip area also decreases. A one-stage amplifier is firstly implemented for helping verifying the de-embedding results. After that a four-stage 60 GHz amplifier has been fabricated in CMOS 65 nm process. Experimental results show that the four-stage amplifier realizes an input matching better than -10.5 dB and an output matching better than -13 dB at 61 GHz. A small signal power gain of 16.4 dB and a 1 dB output compression point of 4.6 dBm are obtained with a DC current consumption of 128 mA from a 1.2 V power supply. The chip size is 1.5 mm 0.85 mm.