An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit
Summary :
In this paper, we propose an optimization system with parallel processing for reducing electromagnetic interference (EMI) on electronic control unit (ECU). We adopt simulated annealing (SA), genetic algorithm (GA) and taboo search (TS) to seek optimal solutions, and a Spice-like circuit simulator to analyze common-mode current. Therefore, the proposed system can determine the adequate combinations of the parasitic inductance and capacitance values on printed circuit board (PCB) efficiently and practically, to reduce EMI caused by the common-mode current. Finally, we apply the proposed system to an example circuit to verify the validity and efficiency of the system.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.6 pp.827-834
- Publication Date
- 2010/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.827
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yuji OKAZAKI, Takanori UNO, Hideki ASAI, "An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 6, pp. 827-834, June 2010, doi: 10.1587/transele.E93.C.827.
Abstract: In this paper, we propose an optimization system with parallel processing for reducing electromagnetic interference (EMI) on electronic control unit (ECU). We adopt simulated annealing (SA), genetic algorithm (GA) and taboo search (TS) to seek optimal solutions, and a Spice-like circuit simulator to analyze common-mode current. Therefore, the proposed system can determine the adequate combinations of the parasitic inductance and capacitance values on printed circuit board (PCB) efficiently and practically, to reduce EMI caused by the common-mode current. Finally, we apply the proposed system to an example circuit to verify the validity and efficiency of the system.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.827/_p
Copy
@ARTICLE{e93-c_6_827,
author={Yuji OKAZAKI, Takanori UNO, Hideki ASAI, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit},
year={2010},
volume={E93-C},
number={6},
pages={827-834},
abstract={In this paper, we propose an optimization system with parallel processing for reducing electromagnetic interference (EMI) on electronic control unit (ECU). We adopt simulated annealing (SA), genetic algorithm (GA) and taboo search (TS) to seek optimal solutions, and a Spice-like circuit simulator to analyze common-mode current. Therefore, the proposed system can determine the adequate combinations of the parasitic inductance and capacitance values on printed circuit board (PCB) efficiently and practically, to reduce EMI caused by the common-mode current. Finally, we apply the proposed system to an example circuit to verify the validity and efficiency of the system.},
keywords={},
doi={10.1587/transele.E93.C.827},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - An Optimization System with Parallel Processing for Reducing Common-Mode Current on Electronic Control Unit
T2 - IEICE TRANSACTIONS on Electronics
SP - 827
EP - 834
AU - Yuji OKAZAKI
AU - Takanori UNO
AU - Hideki ASAI
PY - 2010
DO - 10.1587/transele.E93.C.827
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2010
AB - In this paper, we propose an optimization system with parallel processing for reducing electromagnetic interference (EMI) on electronic control unit (ECU). We adopt simulated annealing (SA), genetic algorithm (GA) and taboo search (TS) to seek optimal solutions, and a Spice-like circuit simulator to analyze common-mode current. Therefore, the proposed system can determine the adequate combinations of the parasitic inductance and capacitance values on printed circuit board (PCB) efficiently and practically, to reduce EMI caused by the common-mode current. Finally, we apply the proposed system to an example circuit to verify the validity and efficiency of the system.
ER -
English
