A dual-mode, triple-band RF front-end receiver for GSM900, DCS1800 and WCDMA is presented in this paper. This chip uses low-IF and zero-IF receiver architectures for GSM and WCDMA respectively to fulfill the entirely different system requirements of the two standards. It consists of three parallel LNAs and down-conversion mixers with on-chip LO I/Q generations. The receiver front-end is implemented in a standard 0.25 µm CMOS process and consumes about 30-mA from a 2.7-V power supply for all modes. The measured double-side band noise figure and voltage gain are 3 dB, 36 dB for the GSM900, 5.9 dB, 31 dB for the DCS1800, and 4.3 dB, 29.6 dB for the WCDMA, respectively.

A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SFT) for V-band applications is designed, fabricated and measured using 0.13-µm CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SFT. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20 GHz. The fabricated receiver has a maximum conversion gain of 19.4 dB, a minimum single-side band noise figure of 10.2 dB, the input-referred 1-dB compression point of -20 dBm and the input third order inter-modulation intercept point of -8.3 dB. It draws only 15.8 mA from a 1.2-V power supply with a total chip area of 0.794 mm0.794 mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.