An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications

Po-Hung CHEN; Min-Chiao CHEN; Chun-Lin KO; Chung-Yu WU

doi:10.1587/transele.E93.C.877

An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications

Po-Hung CHEN, Min-Chiao CHEN, Chun-Lin KO, Chung-Yu WU

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A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SFT) for V-band applications is designed, fabricated and measured using 0.13-µm CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SFT. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20 GHz. The fabricated receiver has a maximum conversion gain of 19.4 dB, a minimum single-side band noise figure of 10.2 dB, the input-referred 1-dB compression point of -20 dBm and the input third order inter-modulation intercept point of -8.3 dB. It draws only 15.8 mA from a 1.2-V power supply with a total chip area of 0.794 mm0.794 mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.

Publication: IEICE TRANSACTIONS on Electronics Vol.E93-C No.6 pp.877-883

Publication Date: 2010/06/01

Publicized

Online ISSN: 1745-1353

DOI: 10.1587/transele.E93.C.877

Type of Manuscript: PAPER

Category: Microwaves, Millimeter-Waves

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Po-Hung CHEN, Min-Chiao CHEN, Chun-Lin KO, Chung-Yu WU, "An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications" in IEICE TRANSACTIONS on Electronics, vol. E93-C, no. 6, pp. 877-883, June 2010, doi: 10.1587/transele.E93.C.877.
Abstract: A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SFT) for V-band applications is designed, fabricated and measured using 0.13-µm CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SFT. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20 GHz. The fabricated receiver has a maximum conversion gain of 19.4 dB, a minimum single-side band noise figure of 10.2 dB, the input-referred 1-dB compression point of -20 dBm and the input third order inter-modulation intercept point of -8.3 dB. It draws only 15.8 mA from a 1.2-V power supply with a total chip area of 0.794 mm0.794 mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.877/_p

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@ARTICLE{e93-c_6_877,
author={Po-Hung CHEN, Min-Chiao CHEN, Chun-Lin KO, Chung-Yu WU, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications},
year={2010},
volume={E93-C},
number={6},
pages={877-883},
abstract={A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SFT) for V-band applications is designed, fabricated and measured using 0.13-µm CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SFT. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20 GHz. The fabricated receiver has a maximum conversion gain of 19.4 dB, a minimum single-side band noise figure of 10.2 dB, the input-referred 1-dB compression point of -20 dBm and the input third order inter-modulation intercept point of -8.3 dB. It draws only 15.8 mA from a 1.2-V power supply with a total chip area of 0.794 mm0.794 mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.},
keywords={},
doi={10.1587/transele.E93.C.877},
ISSN={1745-1353},
month={June},}

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TY - JOUR
TI - An Integrated CMOS Front-End Receiver with a Frequency Tripler for V-Band Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 877
EP - 883
AU - Po-Hung CHEN
AU - Min-Chiao CHEN
AU - Chun-Lin KO
AU - Chung-Yu WU
PY - 2010
DO - 10.1587/transele.E93.C.877
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2010
AB - A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SFT) for V-band applications is designed, fabricated and measured using 0.13-µm CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SFT. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20 GHz. The fabricated receiver has a maximum conversion gain of 19.4 dB, a minimum single-side band noise figure of 10.2 dB, the input-referred 1-dB compression point of -20 dBm and the input third order inter-modulation intercept point of -8.3 dB. It draws only 15.8 mA from a 1.2-V power supply with a total chip area of 0.794 mm0.794 mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.
ER -