An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology
Summary :
An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E93-C No.6 pp.820-826
- Publication Date
- 2010/06/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E93.C.820
- Type of Manuscript
- Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
- Category
Authors
Tetsuro MATSUNO
Daisuke FUJIMOTO
Daisuke KOSAKA
Naoyuki HAMANISHI
Ken TANABE
Masazumi SHIOCHI
Makoto NAGATA
Keyword
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Tetsuro MATSUNO, Daisuke FUJIMOTO, Daisuke KOSAKA, Naoyuki HAMANISHI, Ken TANABE, Masazumi SHIOCHI, Makoto NAGATA, "An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology" in IEICE TRANSACTIONS on Electronics,
vol. E93-C, no. 6, pp. 820-826, June 2010, doi: 10.1587/transele.E93.C.820.
Abstract: An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E93.C.820/_p
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@ARTICLE{e93-c_6_820,
author={Tetsuro MATSUNO, Daisuke FUJIMOTO, Daisuke KOSAKA, Naoyuki HAMANISHI, Ken TANABE, Masazumi SHIOCHI, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology},
year={2010},
volume={E93-C},
number={6},
pages={820-826},
abstract={An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.},
keywords={},
doi={10.1587/transele.E93.C.820},
ISSN={1745-1353},
month={June},}
Copy
TY - JOUR
TI - An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 820
EP - 826
AU - Tetsuro MATSUNO
AU - Daisuke FUJIMOTO
AU - Daisuke KOSAKA
AU - Naoyuki HAMANISHI
AU - Ken TANABE
AU - Masazumi SHIOCHI
AU - Makoto NAGATA
PY - 2010
DO - 10.1587/transele.E93.C.820
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E93-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2010
AB - An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm2 in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes.
ER -
English
