The scaled down feature size and the increased frequency of today's deep sub-micron region call for fundamental changes in driver-load models. To be more specific, new driver-load models need to take into consideration the nonlinear behavior of the drivers, the inductance effects of the loads, and the slew rates of the output waveforms. Current driver-load models use the conventional single Ceff (one-ramp) approach and treat the interconnect load as lumped RC networks. Neither the nonlinear property nor the inductance effects were considered. The accuracy of these existing models is therefore questionable. This paper introduces a new multi-ramp driver model that represents the interconnect load as a distributed RLC network. The employed two effective capacitance values capture the nonlinear behavior of the driver. The lossy transmission line approach accounts for the impact of inductance when modeling the driving point interconnect load. The new model shows improvements of 9% in the average delay error and 2.2% in the slew rate error compared to SPICE.

With the scaling down of CMOS devices, process variation is becoming the leading cause of CMOS based analog circuit failures. For example, a mere 5% variation in feature size can trigger circuit failure. Various methods such as Monte-Carlo and corner-based verification help predict variation caused problems at the expense of thousands of simulations before capturing the problem. This paper presents a new methodology for analog circuit performance prediction. The new method first applies statistical uncertainty analysis on all associated devices in the circuit. By evaluating the uncertainty importance of parameter variability, it approximates the circuit with only components that are most critical to output results. Applying Chebyshev Affine Arithmetic (CAA) on the resulting system provides both performance bounds and probability information in time domain and frequency domain.