This paper presents a triple-band WCDMA direct conversion receiver (DCR) IC that needs a small number of off-chip components and control signals from digital baseband (DBB) IC. The DCR IC consists of 3 quadrature demodulators (QDEMs) with on-chip impedance matching circuit and an analog baseband block (ABB) that contains a low-pass filter (LPF) with fc automatic tuning circuit using no off-chip components and a linear-in-dB variable-gain amplifier (VGA) with on-chip analog high-pass filter (HPF). In order to make use of DBB control-free DC offset canceler, the DCR is designed to avoid large gain change under large interference that causes long transient response. In order to realize that characteristic without increasing quiescent current, the QDEM is used that employs class AB input stage and low-noise common mode feedback (CMFB) output stage. The DCR IC was fabricated in a SiGe BiCMOS process and occupies about 2.9 mm3.0 mm. The DCR needs SAW filters only for off-chip components and a gain control signal from DBB IC for AGC loop. The IIP3 of over -4.4 dBm for small signal input level and that of over +1.9 dBm for large signal input level are achieved. The gain compression of the desired signal is less than 0.3 dB for ACS Case-II condition.

A fast fc automatic tuning circuit suitable for WCDMA systems is proposed. The circuit employs master-slave architecture using digitally controlled Gm-C filter for avoiding long transient response. The tuning feedback loop contains a 2-bit up-down counter ADC for fast tuning operation. Furthermore, to avoid degradation of fc tuning accuracy due to reference feedthrough, an analog loop filter with notch located near reference frequency is used. The fast fc automatic tuning circuit is fabricated in a SiGe BiCMOS process. The tuning time within 200 µs is achieved for 35 chips from 2 lots and the standard deviation of 25.5 kHz is obtained for the average fc of 2.12 MHz.

An operational amplifier is one of the key functional blocks and is widely used in analog and mixed-signal circuits. For low-power consumption, many techniques such as class AB and slew-rate enhancement have been proposed. Although phase compensation is related to power consumption, it has not been clearly discussed from the viewpoint of the power consumption. In this paper, the conventional and the improved Miller compensations and the phase compensation by introducing a new zero are dicussed for low-power operational amplifiers.

A novel automatic quality factor (Q) tuning scheme for an low-power and wideband active-RC filter is presented. Although Q-tuning is effective to reduce the power consumption of wideband active-RC filters, there are several problems since the Q-tuning normally relies on a magnitude locked loop (MLL). MLL is not accurate due to the amplitude detection circuits, and occupied area and power consumption tends to be large due to its complexity. In addition, flexibility to the reference signal may be the problem, since the reference signal which has a fixed accurate frequency is required. In order to solve these problems, we propose a Q-tuning scheme, which does not require a MLL. Therefore, proposed Q-tuning scheme has good accuracy, small die area, low power consumption and flexibility to the reference signal. In our proposed scheme, Q is tuned by adjusting the phase of an integrator to 90 degrees. The phase of an integrator is adjusted by detecting and controlling the oscillation frequency of a two-stage ring-integrator to the cutoff frequency of a filter, since the phase shift of an integrator is exactly 90 degrees at the oscillation frequency. The frequency is easily detected and controlled by counters and variable resistors, respectively. The Q-tuning circuit with a 5th-order Chebyshev LPF is implemented in a 0.13 µm CMOS technology. The tuning circuit occupies 0.12 mm2 and consumes 2.6 mW from 1.2 V supply.

In a direct conversion receiver for mobile communication, it is important to reduce power dissipation. Because a low pass filter in a direct conversion receiver must suppress adjacent channel signals, a high order and high power dissipation is often required in the low pass filter. We propose a new phase compensation technique suitable for a low power transconductor used in a GmC filter as a low pass filter. The new phase compensation technique reduces 10% of power dissipation.

A wideband, low noise, and highly linear transmitter for multi-mode radio is presented. Envelope injection scheme with a CMOS amplifier is developed to obtain sufficient linearity for complex modulation schemes such as OFDM, and to achieve low noise for concurrent operation of more than one standard. Active matching technique with doubly terminated LPF topology is also presented to realize wide bandwidth, low power consumption, and to eliminate off-chip components without increasing die area. A multi-mode transmitter is implemented in a 0.13 µm CMOS technology with an active area of 1.13 mm2. Third-order intermodulation product is improved by 17 dB at -3 dBm output by the envelope injection scheme. The transmitter achieves EVM of less than -29.5 dB at -3 dBm output from 0.2 to 7.2 GHz while consuming only 69 mW. The transmitter is also tested with multiple standards of UMTS, 802.11b, WiMax, 802.11a, and 802.11n, and satisfies EVM, ACLR, and spectrum specifications.

A direct conversion receiver for W-CDMA, which consumes extremely low power, is presented. The receiver consists of a low-noise amplifier (LNA) IC, a receiver IC and other passive components such as an RF-SAW (Surface Acoustic Wave) filter. The receiver IC includes a quadrature demodulator (QDEM) with a local oscillator (LO) divider, low-pass filters (LPFs) for channel selection, variable gain amplifiers (VGAs) with dynamic range of 80 dB, and a fractional-N synthesizer. The power consumption for the entire receiver chain was only 30.8 mA at supply voltage of 2.7 V.