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[Author] Junji WADATSUMI(2hit)

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  • A Low-Noise and Highly-Linear Transmitter with Envelope Injection Pre-Power Amplifier for Multi-Mode Radio

    Shouhei KOUSAI  Daisuke MIYASHITA  Junji WADATSUMI  Rui ITO  Takahiro SEKIGUCHI  Mototsugu HAMADA  Kenichi OKADA  

     
    PAPER

      Vol:
    E94-A No:2
      Page(s):
    592-602

    A wideband, low noise, and highly linear transmitter for multi-mode radio is presented. Envelope injection scheme with a CMOS amplifier is developed to obtain sufficient linearity for complex modulation schemes such as OFDM, and to achieve low noise for concurrent operation of more than one standard. Active matching technique with doubly terminated LPF topology is also presented to realize wide bandwidth, low power consumption, and to eliminate off-chip components without increasing die area. A multi-mode transmitter is implemented in a 0.13 µm CMOS technology with an active area of 1.13 mm2. Third-order intermodulation product is improved by 17 dB at -3 dBm output by the envelope injection scheme. The transmitter achieves EVM of less than -29.5 dB at -3 dBm output from 0.2 to 7.2 GHz while consuming only 69 mW. The transmitter is also tested with multiple standards of UMTS, 802.11b, WiMax, 802.11a, and 802.11n, and satisfies EVM, ACLR, and spectrum specifications.

  • A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver Open Access

    Fumihiko TACHIBANA  Huy CU NGO  Go URAKAWA  Takashi TOI  Mitsuyuki ASHIDA  Yuta TSUBOUCHI  Mai NOZAWA  Junji WADATSUMI  Hiroyuki KOBAYASHI  Jun DEGUCHI  

     
    PAPER

      Pubricized:
    2023/11/02
      Vol:
    E107-A No:5
      Page(s):
    709-718

    Although baud-rate clock and data recovery (CDR) such as Mueller-Müller (MM) CDR is adopted to ADC-based receivers (RXs), it suffers from false-lock points when the RXs handle PAM4 data pattern because of the absence of edge data. In this paper, a false-lock-aware locking scheme is proposed to address this issue. After the false-lock-aware locking scheme, a clock phase is adjusted to achieve maximum eye height by using a post-1-tap parameter for an FFE in the CDR loop. The proposed techniques are implemented in a 56-Gb/s PAM4 transceiver. A PLL uses an area-efficient “glasses-shaped” inductor. The RX comprises an AFE, a 28-GS/s 7-bit time-interleaved SAR ADC, and a DSP with a 31-tap FFE and a 1-tap DFE. A TX is based on a 7-bit DAC with a 4-tap FFE. The transceiver is fabricated in 16-nm CMOS FinFET technology, and achieves a BER of less than 1e-7 with a 30-dB loss channel. The measurement results show that the MM CDR escapes from false-lock points, and converges to near the optimum point for large eye height.