Although baud-rate clock and data recovery (CDR) such as Mueller-Müller (MM) CDR is adopted to ADC-based receivers (RXs), it suffers from false-lock points when the RXs handle PAM4 data pattern because of the absence of edge data. In this paper, a false-lock-aware locking scheme is proposed to address this issue. After the false-lock-aware locking scheme, a clock phase is adjusted to achieve maximum eye height by using a post-1-tap parameter for an FFE in the CDR loop. The proposed techniques are implemented in a 56-Gb/s PAM4 transceiver. A PLL uses an area-efficient “glasses-shaped” inductor. The RX comprises an AFE, a 28-GS/s 7-bit time-interleaved SAR ADC, and a DSP with a 31-tap FFE and a 1-tap DFE. A TX is based on a 7-bit DAC with a 4-tap FFE. The transceiver is fabricated in 16-nm CMOS FinFET technology, and achieves a BER of less than 1e-7 with a 30-dB loss channel. The measurement results show that the MM CDR escapes from false-lock points, and converges to near the optimum point for large eye height.

Intending to contribute to constructing better multimedia network systems, we propose a new concept of image database system of which form of storage is featuring exponential or graceful oblivion and abrupt recollection like the human memory property. By virtue of this property of database storages that is realized by employing hierarchical or pyramidal image coding, the database memory and transmission costs can be significantly reduced. In this paper we will describe the details of the concept, the results of theoretical analysis based on a simplified model which reveals the effectiveness of the proposed system, the structure of an experimental prototype system and the result of an experimental image retrieval service carried out by implementing it over ATM high speed channels.