This paper proposes a power supply voltage control technique, and demonstrates its effectiveness for eliminating the overkills and underkills due to the power supply characteristic difference between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method controls the static power supply voltage on the ATE system, so that the ATE can eliminate misjudges for the Pass or Fail of the DUT. The method for calculating the power supply voltage is also described. Experimental results show that the proposed method can eliminate 89% of overkills and underkills in delay fault testing with 105 real silicon devices. Limitations of the proposed method are also discussed.
Masahiro ISHIDA
ADVANTEST Corporation
Toru NAKURA
University of Tokyo
Takashi KUSAKA
ADVANTEST Corporation
Satoshi KOMATSU
Tokyo Denki University
Kunihiro ASADA
University of Tokyo
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Masahiro ISHIDA, Toru NAKURA, Takashi KUSAKA, Satoshi KOMATSU, Kunihiro ASADA, "Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 10, pp. 1219-1225, October 2016, doi: 10.1587/transele.E99.C.1219.
Abstract: This paper proposes a power supply voltage control technique, and demonstrates its effectiveness for eliminating the overkills and underkills due to the power supply characteristic difference between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method controls the static power supply voltage on the ATE system, so that the ATE can eliminate misjudges for the Pass or Fail of the DUT. The method for calculating the power supply voltage is also described. Experimental results show that the proposed method can eliminate 89% of overkills and underkills in delay fault testing with 105 real silicon devices. Limitations of the proposed method are also discussed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.1219/_p
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@ARTICLE{e99-c_10_1219,
author={Masahiro ISHIDA, Toru NAKURA, Takashi KUSAKA, Satoshi KOMATSU, Kunihiro ASADA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing},
year={2016},
volume={E99-C},
number={10},
pages={1219-1225},
abstract={This paper proposes a power supply voltage control technique, and demonstrates its effectiveness for eliminating the overkills and underkills due to the power supply characteristic difference between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method controls the static power supply voltage on the ATE system, so that the ATE can eliminate misjudges for the Pass or Fail of the DUT. The method for calculating the power supply voltage is also described. Experimental results show that the proposed method can eliminate 89% of overkills and underkills in delay fault testing with 105 real silicon devices. Limitations of the proposed method are also discussed.},
keywords={},
doi={10.1587/transele.E99.C.1219},
ISSN={1745-1353},
month={October},}
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TY - JOUR
TI - Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing
T2 - IEICE TRANSACTIONS on Electronics
SP - 1219
EP - 1225
AU - Masahiro ISHIDA
AU - Toru NAKURA
AU - Takashi KUSAKA
AU - Satoshi KOMATSU
AU - Kunihiro ASADA
PY - 2016
DO - 10.1587/transele.E99.C.1219
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2016
AB - This paper proposes a power supply voltage control technique, and demonstrates its effectiveness for eliminating the overkills and underkills due to the power supply characteristic difference between an automatic test equipment (ATE) and a practical operating environment of the DUT. The proposed method controls the static power supply voltage on the ATE system, so that the ATE can eliminate misjudges for the Pass or Fail of the DUT. The method for calculating the power supply voltage is also described. Experimental results show that the proposed method can eliminate 89% of overkills and underkills in delay fault testing with 105 real silicon devices. Limitations of the proposed method are also discussed.
ER -