Chip-Level Substrate Coupling Analysis with Reference Structures for Verification

Daisuke KOSAKA; Makoto NAGATA; Yoshitaka MURASAKA; Atsushi IWATA

doi:10.1093/ietfec/e90-a.12.2651

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification

Daisuke KOSAKA, Makoto NAGATA, Yoshitaka MURASAKA, Atsushi IWATA

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Chip-level substrate coupling analysis uses F-matrix computation with slice-and-stack execution to include highly concentrated substrate resistivity gradient. The technique that has been applied to evaluation of device-level isolation structures against substrate coupling is now developed into chip-level substrate noise analysis. A time-series divided parasitic capacitance (TSDPC) model is equivalent to a transition controllable noise source (TCNS) circuit that captures noise generation in a CMOS digital circuit. A reference structure incorporating TCNS circuits and an array of on-chip high precision substrate noise monitors provides a basis for the verification of chip-level analysis of substrate coupling in a given technology. Test chips fabricated in two different wafer processings of 0.30-µm and 0.18-µm CMOS technologies demonstrate the universal availability of the proposed analysis techniques. Substrate noise simulation achieves no more than 3 dB discrepancy in peak amplitude compared to measurements with 100-ps/100-µV resolution, enabling precise evaluation of the impacts of the distant placements of sensitive devices from sources of noise as well as application of guard ring/band structures.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E90-A No.12 pp.2651-2660

Publication Date: 2007/12/01

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Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e90-a.12.2651

Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

Category: Physical Design

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Daisuke KOSAKA, Makoto NAGATA, Yoshitaka MURASAKA, Atsushi IWATA, "Chip-Level Substrate Coupling Analysis with Reference Structures for Verification" in IEICE TRANSACTIONS on Fundamentals, vol. E90-A, no. 12, pp. 2651-2660, December 2007, doi: 10.1093/ietfec/e90-a.12.2651.
Abstract: Chip-level substrate coupling analysis uses F-matrix computation with slice-and-stack execution to include highly concentrated substrate resistivity gradient. The technique that has been applied to evaluation of device-level isolation structures against substrate coupling is now developed into chip-level substrate noise analysis. A time-series divided parasitic capacitance (TSDPC) model is equivalent to a transition controllable noise source (TCNS) circuit that captures noise generation in a CMOS digital circuit. A reference structure incorporating TCNS circuits and an array of on-chip high precision substrate noise monitors provides a basis for the verification of chip-level analysis of substrate coupling in a given technology. Test chips fabricated in two different wafer processings of 0.30-µm and 0.18-µm CMOS technologies demonstrate the universal availability of the proposed analysis techniques. Substrate noise simulation achieves no more than 3 dB discrepancy in peak amplitude compared to measurements with 100-ps/100-µV resolution, enabling precise evaluation of the impacts of the distant placements of sensitive devices from sources of noise as well as application of guard ring/band structures.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e90-a.12.2651/_p

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@ARTICLE{e90-a_12_2651,
author={Daisuke KOSAKA, Makoto NAGATA, Yoshitaka MURASAKA, Atsushi IWATA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Chip-Level Substrate Coupling Analysis with Reference Structures for Verification},
year={2007},
volume={E90-A},
number={12},
pages={2651-2660},
abstract={Chip-level substrate coupling analysis uses F-matrix computation with slice-and-stack execution to include highly concentrated substrate resistivity gradient. The technique that has been applied to evaluation of device-level isolation structures against substrate coupling is now developed into chip-level substrate noise analysis. A time-series divided parasitic capacitance (TSDPC) model is equivalent to a transition controllable noise source (TCNS) circuit that captures noise generation in a CMOS digital circuit. A reference structure incorporating TCNS circuits and an array of on-chip high precision substrate noise monitors provides a basis for the verification of chip-level analysis of substrate coupling in a given technology. Test chips fabricated in two different wafer processings of 0.30-µm and 0.18-µm CMOS technologies demonstrate the universal availability of the proposed analysis techniques. Substrate noise simulation achieves no more than 3 dB discrepancy in peak amplitude compared to measurements with 100-ps/100-µV resolution, enabling precise evaluation of the impacts of the distant placements of sensitive devices from sources of noise as well as application of guard ring/band structures.},
keywords={},
doi={10.1093/ietfec/e90-a.12.2651},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Chip-Level Substrate Coupling Analysis with Reference Structures for Verification
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2651
EP - 2660
AU - Daisuke KOSAKA
AU - Makoto NAGATA
AU - Yoshitaka MURASAKA
AU - Atsushi IWATA
PY - 2007
DO - 10.1093/ietfec/e90-a.12.2651
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E90-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2007
AB - Chip-level substrate coupling analysis uses F-matrix computation with slice-and-stack execution to include highly concentrated substrate resistivity gradient. The technique that has been applied to evaluation of device-level isolation structures against substrate coupling is now developed into chip-level substrate noise analysis. A time-series divided parasitic capacitance (TSDPC) model is equivalent to a transition controllable noise source (TCNS) circuit that captures noise generation in a CMOS digital circuit. A reference structure incorporating TCNS circuits and an array of on-chip high precision substrate noise monitors provides a basis for the verification of chip-level analysis of substrate coupling in a given technology. Test chips fabricated in two different wafer processings of 0.30-µm and 0.18-µm CMOS technologies demonstrate the universal availability of the proposed analysis techniques. Substrate noise simulation achieves no more than 3 dB discrepancy in peak amplitude compared to measurements with 100-ps/100-µV resolution, enabling precise evaluation of the impacts of the distant placements of sensitive devices from sources of noise as well as application of guard ring/band structures.
ER -