This paper proposes an efficient reduction method for a substrate network model, which is extracted from layout data, to analize a substrate coupling noise. The proposed method adopts in a reduction operation a hierarchic structure of a substrate RC network model, a computational procedure using matrix elements, and an expression of admittance as polynominal in complex frequency s=jω. These techniques improve computational efficiency and are suitable for an implementation. In the example of a triple well CMOS circuit, a reduced model, from 7500 nodes to 5 nodes, has less than 25% errors up to 1 GHz.

Multilayer feedforward neural network (MFNN) trained by the backpropagation (BP) algorithm is one of the most significant models in artificial neural networks. MFNNs have been used in many areas of signal and image processing due to high applicability. Although they have been implemented as analog, mixed analog-digital and fully digital VLSI circuits, it is still difficult to realize their hardware implementation with the BP learning function efficiently. This paper describes a special BP algorithm for the logic oriented neural network (LOGO-NN) which we have proposed as a sort of MFNN with quantized weights and multilevel threshold neurons. Both weights and neuron outputs are quantized to integer values in LOGO-NNs. Furthermore, the proposed BP algorithm can reduce high precise calculations. Therefore, it is expected that LOGO-NNs with BP learning can be more effectively implemented as digital type circuits than the common MFNNs with the classical BP. Finally, it is shown by simulations that the proposed BP algorithm for LOGO-NNs has good performance in terms of the convergence rate, convergence speed and generalization capability.

Equivalent-time sampling is a well-known technique to capture repetitive signals at finer time intervals than a sampling clock cycle time and it is widely used to implement waveform measurement with high time resolution. There are three techniques for implementing its time base (i.e., sequential sampling, random sampling and coherent sampling), and they have their respective advantages and disadvantages. In this paper we propose a new coherent sampling system which incorporates a pretrigger and time jitter reduction function for a fluctuating input signal which a random sampling system has, while maintaining the waveform recording efficiency of a conventional coherent sampling system. We also report on a technique for measuring a reference trigger time period accurately which is necessary to implement the proposed sampling system, and show its effectiveness through numerical calculations of its data recording time.

Processes in image recognition include target detection and shape extraction. Active Net has been proposed as one of the methods for such processing. It treats the target detection in an image as an energy optimization problem. In this paper, a problem of the conventional Active Net is presented and the new Active Net is proposed. The new net is improved the ability for detecting a target. Finally, the validity of the proposed net is confirmed by experimental results.

This paper presents a method of statistical system optimization. The method uses a constraint generation, which is a design methodology based on a hierarchical top-down design, to give specifications to sub-circuits of the system. The specifications are generated not only to reduce the costs of sub-circuits but also to take adequate margin to achieve enough yield of the system. In order to create an appropriate amount of margin, a term which expresses a statistical figure based on Mahalanobis' distance is added to the constraint generation problem. The method is applied to a PLL, and it is confirmed that the yield of the lock-up time reaches 100% after the optimization.

In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.

A new architecture-based Dynamically Programmable Arithmetic Array processor (DPAA) is proposed for general purpose Digital Signal Processing applications. Parallelism and pipelining are achieved by using DPAA, which consists of various basic arithmetic blocks connected through a code-division multiple access bus interface. The proposed architecture poses 100% interconnection flexibility because connections are done virtually through code matching instead of physical wire connections. Compared to conventional multiplexing architectures, the proposed interconnection topology consumes less chip area and thus, more arithmetic blocks can be incorporated. A 16-bit prototype chip incorporating 10 multipliers and 40 other arithmetic blocks had been implemented into a 4.5 mm 4.5 mm chip with 0.6 µm CMOS process. DPAA also features its simple programmability, as numerical formula can be used to configure the processor without programming languages or specialized CAD tools.

In this paper, an architecture of multi-threaded processor for embedded systems is proposed and evaluated comparing with other processors for embedded systems. The experimental results show the trade-off of hardware costs and execution times among processors. Taking proposed multi-threaded processor into account as an embedded processor, design space of embedded systems are enlarged and more suitable architecture can be selected under some design constraints.

This paper aims at improving effectiveness of previously proposed hybrid priority lists, {L^*_i=L_dL_si}, that are applied in nonpreemptive 2-processor scheduling of general acyclic SWITCH-less program nets, where L_d and L_si are dynamic and static priority lists respectively. Firstly, we investigate the effectiveness of L_d through experiments. According to the experimental results, we reconstruct L_d to propose its improved list L¹_d. Then analyzing the construction methodology of the static priority lists {L_si}, we propose a substituted list L²_d by taking into account of the factor: remaining firing numbers of nodes. Finally, we combine a part of L¹_d and L²_d to propose a new priority list L^**. Through scheduling simulation on 400 program nets, we find the new priority list L^** can generate shorter schedules, close to ones of GA (Genetic Algorithm) scheduling that has been shown exceedingly effective but costing much computation time.

Autonomous distributed scheduling is based on the autonomous decentralized optimization and recently focused as one of flexible scheduling techniques which can more cope with dynamically changing situation than traditional ones. This paper proposes an autonomous distributed scheduling scheme for the parallel machine scheduling problem. Through computer simulation, we observe that our proposed scheme can more quickly reduce the total deadline over-time than one in the literature and can adapt flexibly to unusual situation (addition of jobs).

This paper proposes a new heuristic algorithm FMDB for the minimum initial marking problem MIM of Petri nets: "Given a Petri net and a firing count vector X, find an initial marking M₀, with the minimum total token number, for which there is a sequence δ of transitions such that each transition t appears exactly X(t) times in δ, the first transition is firable on M₀ and the rest can be fired one by one subsequently. " Experimental results show that FMDB produces better solutions than any known algorithm.

The k-vertex-connectivity augmentation problem for a specified set of vertices of a graph with degree-unchangeable vertices, kVCA(G,S,D), is defined as follows: "Given a positive integer k, an undirected graph G=(V,E), a specified set of vertices S V and a set of degree-changeable vertices D V, find a smallest set of edges E such that the vertex-connectivity of S in (V,E E) is at least k and E {(u,v) u,v D}. " The main result of the paper is that checking the existence of a solution and finding a solution to 2VCA(G,S,D) or 3VCA(G,S,D) can be done in O(|V|+|E|) or O(|V|(|V|+|E|)) time, respectively.

In the culture of marine chlorellas, it is necessary to count the number in order to understand the condition of increase. For that propose, counting by the naked eye using the microscope has been used. However, this method requires a lot of time and work. We have developed the automatic chlorella counter using image processing and neural network. Its effectiveness is confirmed through the experiment.

Most natural images are well modeled as smoothed areas segmented by edges. The smooth areas can be well represented by a wavelet transform with high regularity and with fewer coefficients which requires highpass filters with some vanishing moments. However for the regions around edges, short highpass filters are preferable. In one recently proposed approach, this problem was solved by switching filter banks using longer filters for smoothed areas of the images and shorter filters for areas with edges. This approach was applied to lossy image coding resulting in a reduction of ringing artifacts. As edges were predicted using neighboring pixels, the nonlinear transforms made the decorrelation more flexible. In this paper we propose a time-varying filterbank and apply it to lossless image coding. In this scheme, we estimate the standard deviation of the neighboring pixels of the current pixel by solving the maximum likelihood problem. The filterbank is switched between three filter banks, depending on the estimated standard deviation.

For the purpose of equalisation of rapidly time variant multipath channels, we derive a novel adaptive algorithm, the amplitude banded LMS (ABLMS), which implements a non-linear adaptation based on a coefficient matrix. Then we develop the ABLMS algorithm as the adaptation procedure for a linear transversal equaliser (LTE) and a decision feedback equaliser (DFE) where a parallel adaptation scheme is deployed. Computer simulations demonstrate that with a small increase of computational complexity, the ABLMS based parallel equalisers provide a significant improvement related to the conventional LMS DFE and the LMS LTE in the case of a second order Markov communication channel model.

Optimization procedure on higher order Delta-sigma (ΔΣ) modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR (Signal to Noise Ratio) degradation. The optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm, and remains the stable input limit satisfies the original design requirement.

This paper is concerned with fuzzy modeling in some reduction methods of inference rules with gradient descent. Reduction methods are presented, which have a reduction mechanism of the rule unit that is applicable in three parameters--the central value and the width of the membership function in the antecedent part, and the real number in the consequent part--which constitute the standard fuzzy system. In the present techniques, the necessary number of rules is set beforehand and the rules are sequentially deleted to the prespecified number. These methods indicate that techniques other than the reduction approach introduced previously exist. Experimental results are presented in order to show that the effectiveness differs between the proposed techniques according to the average inference error and the number of learning iterations.

This paper presents a new performance and routability-driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). The contribution of our work is to overcome one of the most critical limitations of the previous routing algorithms: inaccurate estimations of routing density which were too general for symmetrical FPGA. To this end, we devised new routing density measures that are directly linked to the structure (switch block) of symmetrical FPGA, and utilize them consistently in global and detailed routings. With the use of the proposed accurate routing metrics, we developed a new routing algorithm called a reliable net decomposition-based routing which is very fast, and yet produces excellent routing results in terms of net/path delays and routability. An extensive experiment was carried out to show the effectiveness of our algorithm based on the proposed cost metrics. In summary, when compared to the best known results in the literature (TRACER-fpga_PR and SEGA), our algorithm has shown 31.9% shorter longest path delay and 23.0% shorter longest net delay even with about 9 times faster execution time.

First, we show that the necessary and sufficient condition for the existence of a balanced bowtie decomposition of the complete tripartite multi-graph λ K_n1,_n2,_n3 is (i) n₁=n₂=n₃ 0 (mod 6) for λ 1,5 (mod 6), (ii) n₁=n₂=n₃ 0 (mod 3) for λ 2,4 (mod 6), (iii) n₁=n₂=n₃ 0 (mod 2) for λ 3 (mod 6), and (iv) n₁=n₂=n₃ 2 for λ 0 (mod 6). Next, we show that the necessary and sufficient condition for the existence of a balanced trefoil decomposition of the complete tripartite multi-graph λ K_n1,_n2,_n3 is (i) n₁=n₂=n₃ 0 (mod 9) for λ 1,2,4,5,7,8 (mod 9), (ii) n₁=n₂=n₃ 0 (mod 3) for λ 3,6 (mod 9), and (iii) n₁=n₂=n₃ 3 for λ 0 (mod 9).

A secret sharing scheme allows a secret to be shared among a set of participants, P, such that only authorized subsets of P can recover the secret, but any unauthorized subset can not recover the secret. It can be used to protect important secret data, such as cryptographic keys, from being lost or destroyed without accidental or malicious exposure. In this paper, we consider secret sharing schemes based on interpolating polynomials. We show that, by simply increasing the number of shares held by each participant, there is a multiple assignment scheme for any monotone access structure such that cheating can be detected with very high probability by any honest participant even the cheaters form a coalition in order to deceive him.

This paper treats weight distributions of the coset leaders of binary linear block codes. We first present a method for computing the weight distribution of the coset leaders of a given code using two tables each of which stores the weights of the coset leaders of a related code of the code. Then, the weight distributions of the coset leaders of the (N,K) Reed-Muller codes, binary primitive BCH codes, and their extended codes with N 128 and 29 N-K 42 that are obtained by using the computing method are given.

Recently, Vatan, Roychowdhury and Anantram have presented two types of revised versions of the Calderbank-Shor-Steane code construction, and have also provided an exhaustive procedure for determining bases of quantum error-correcting codes. In this paper, we investigate the revised versions given by Vatan et al., and point out that there is no essential difference between them. In addition, we propose an efficient algorithm for searching for bases of quantum error-correcting codes. The proposed algorithm is based on some fundamental properties of classical linear codes, and has much lower complexity than Vatan et al.'s procedure.

In this paper, we discuss power spectrum overlapping of wideband/narrowband signals and wideband/wideband signals for increasing transmission efficiency. Here, in order to eliminate cross signal interference among those signals, we propose a generalized zero-forcing type decorrelating detection. Our numerical results show that, with the decorrelating detector, the overlapped wideband/wideband signal transmission can much improve the transmission efficiency. This implies that, for a given frequency bandwidth, in order to increase the information transmission rate, we should employ two different kinds of direct sequence spread spectrum-based signals with each power spectrum appropriately overlapped, not taking a single carrier-based approach nor an orthogonal multi-carrier approach.

A chemical shift MR method which utilizes a oscillating gradient field is presented in this paper. Frequency modulation resulting from oscillating a gradient field spreads the spectrum that contains both chemical shift and spatial information, over a wide frequency range by using a large modulation factor in FM. The chemical shift spectrum resides within every frequency band segmented by the modulation frequency ω_m. The spectral elements gathered from all such frequency segments for a chemical shift frequency contain the spatial image of that particular chemical shift frequency, despite the distortion introduced by a series of the Bessel functions acting as a point spread function. A sum of several Bessel functions of the first kind J_n(. ) is used to approximate the deconvolution process, since the sum staggered with respect to n has a desirable peaking property useful in deconvolution. This leads to devise a new image reconstruction algorithm based on the simple moving average over the spatial coordinate for which the oscillating gradient is applied. Furthermore, the number of echo measurements necessary for an image size of N N is reduced from N² of the spin echo chemical shift imaging down to N by this method. Simulation results supporting the validity of this method are also presented in this paper.

This paper presents a fast algorithm for calculating box splines sampled at regular intervals. This algorithm is based on the representation by directional summations, while splines are often represented by convolutions. The summation-based representation leads less computational complexity: the proposed algorithm requires fewer additions and much fewer multiplications than the algorithm based on convolutions. The proposed algorithm is evaluated in the sense of the number of additions and multiplications for three- and four-directional box splines to see how much those operations are reduced.

Digital watermarking schemes have been discussed to solve the problem associated with copyright enforcement. Previously, we proposed a method using inter-block correlation of DCT coefficients. It has the features that the embedded watermark can be extracted without the original image nor the parameters used in embedding process and that the amount of modification, the strength of embedded watermark, depends on the local feature of an image. This feature makes it difficult for pirate to predict the position in which the watermark signal is embedded. In this paper, we propose a method which can embed/extract watermark with high speed by utilizing this watermarking method for JPEG file format.