IEICE TRANSACTIONS on Fundamentals
A Fine Grain Cooled Logic Architecture for Low-Power Processors
Summary :
In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.3 pp.735-740
- Publication Date
- 2001/03/01
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
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Hiroyuki MATSUBARA, Takahiro WATANABE, Tadao NAKAMURA, "A Fine Grain Cooled Logic Architecture for Low-Power Processors" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 3, pp. 735-740, March 2001, doi: .
Abstract: In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_3_735/_p
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@ARTICLE{e84-a_3_735,
author={Hiroyuki MATSUBARA, Takahiro WATANABE, Tadao NAKAMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Fine Grain Cooled Logic Architecture for Low-Power Processors},
year={2001},
volume={E84-A},
number={3},
pages={735-740},
abstract={In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - A Fine Grain Cooled Logic Architecture for Low-Power Processors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 735
EP - 740
AU - Hiroyuki MATSUBARA
AU - Takahiro WATANABE
AU - Tadao NAKAMURA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2001
AB - In this paper, we propose a fine grain Cooled Logic architecture for low-power oriented processors. Cooled Logic detects, in novel hardware method with dual-rail logic, functional blocks to be active, and stops clocks to each of the functional blocks in order to make it inactive at certain periods. To confirm the effectiveness of our approach, we design a 4-bit and a 16-bit event-driven array multipliers, and analyze their power consumption by the HSPICE simulator. As a result, it is shown that Cooled Logic has a tendency to reduce power consumptions in both the functional blocks and the clock drivers of the multipliers.
ER -
English
