Optimization procedure on higher order Delta-sigma (ΔΣ) modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR (Signal to Noise Ratio) degradation. The optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm, and remains the stable input limit satisfies the original design requirement.

Higher order delta-sigma (ΔΣ) modulator with one bit quantizer is known as one of the easiest method to gain a high resolution A/D converter without the need of accurately matched components. However, stability of higher order ΔΣ modulator is still a problem during the design and implementation process. Stabilizing higher order modulator requires the proper choice of integrator gains. In this paper, a new approach on ΔΣ modulator stability analysis which based on the system auto-correlation function is proposed, and equation of NTF power integration is derived out. The specification of equation related to input signal amplitude and output quantization level is discussed. Combining with system control theory, the stability of higher order modulator (2nd and 3rd order) is evaluated. Matlab simulation confirm the proposed method. It offers an evaluation method for the choice of the in-loop integrator gains which ensure the modulator operates under the stable status, and is able to be used for designing stable higher order ΔΣ analog-to-digital converters.