Higher Order Delta-Sigma AD Converter with Optimized Stable Coefficients
Summary :
Optimization procedure on higher order Delta-sigma (ΔΣ) modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR (Signal to Noise Ratio) degradation. The optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm, and remains the stable input limit satisfies the original design requirement.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.3 pp.813-819
- Publication Date
- 2001/03/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Analog Signal Processing
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yikui ZHANG, Etsuro HAYAHARA, Satoshi HIRANO, "Higher Order Delta-Sigma AD Converter with Optimized Stable Coefficients" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 3, pp. 813-819, March 2001, doi: .
Abstract: Optimization procedure on higher order Delta-sigma (ΔΣ) modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR (Signal to Noise Ratio) degradation. The optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm, and remains the stable input limit satisfies the original design requirement.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_3_813/_p
Copy
@ARTICLE{e84-a_3_813,
author={Yikui ZHANG, Etsuro HAYAHARA, Satoshi HIRANO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Higher Order Delta-Sigma AD Converter with Optimized Stable Coefficients},
year={2001},
volume={E84-A},
number={3},
pages={813-819},
abstract={Optimization procedure on higher order Delta-sigma (ΔΣ) modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR (Signal to Noise Ratio) degradation. The optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm, and remains the stable input limit satisfies the original design requirement.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - Higher Order Delta-Sigma AD Converter with Optimized Stable Coefficients
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 813
EP - 819
AU - Yikui ZHANG
AU - Etsuro HAYAHARA
AU - Satoshi HIRANO
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2001
AB - Optimization procedure on higher order Delta-sigma (ΔΣ) modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR (Signal to Noise Ratio) degradation. The optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm, and remains the stable input limit satisfies the original design requirement.
ER -
English
