Optimization procedure on higher order Delta-sigma (ΔΣ) modulator coefficients is proposed. The procedure is based on the higher order ΔΣ modulator stability judgement method. The application specification can be satisfied with the proposed method. The 4th order modulator examples are illustrated. Optimized coefficients and its behavior model simulation results demonstrated that this methodology is suitable for the design of higher order ΔΣ AD converter. The coefficients tolerance up to 2% is allowed for switched-capacitor implementation, with not more than 3.5 dB SNR (Signal to Noise Ratio) degradation. The optimized coefficients improves 2 to 3 bit of the modulator's resolution than the previous proposed algorithm, and remains the stable input limit satisfies the original design requirement.