In this paper, a methodology for designing the architecture of the processor array for wide class of image processing algorithms is proposed. A concept of spatially expanding the SFG description which enables us to handle the problem as merely one-dimensional signal processing is used in constructing the methodology. Problem of I/O interface which is critical in real-time processing is also considered.

A synthesizable HDL generation method for pipelined processors is proposed. By using the proposed method, data-path and control logic descriptions of a target processor is generated from a clock based instruction set specification. From the experimental results, feasibility of the proposed method is evaluated and the amount of processor design time was drastically reduced than that of conventional RT level manual design in HDL.

In this letter, a new approach to segment depth-of-field (DoF) images is proposed. The methodology is based on a two-stage model of visual neuron. The first stage is a retinal filtering by means of luminance normalizing non-linearity. The second stage is a V1-like filtering using filters estimated by independent component analysis (ICA). Segmented image is generated by the response activity of the neuron measured in terms of kurtosis. Results demonstrate that the model can discriminate image parts in different levels of depth-of-field. Comparison with other methodologies and limitations of the proposed methodology are also presented.

We have developed spectral separation devices for processing femtosecond pulses. These devices are based on an optical coupler structure with fiber gratings. In a computer simulation, we confirmed that these devices could extract <1 nm bandwidth light with 80% efficiency. We fabricated the spectral separation devices using single mode fibers and highly Ge-doped fibers. These devices successfully extracted narrow spectral light of 0.3 nm bandwidth with 37% efficiency from femtosecond pulses of 40 nm bandwidth. We also fabricated 2-channel spectral separation devices, which could extract the light from each grating channel.

We have developed optical encoding devices for processing femtosecond pulses. These devices are based on spectral separation devices and light modulators with fiber gratings. Experiments were made to encode a light pulse in the spectral domain. These experiments utilize the characteristics that a femtosecond light pulse has a very broad spectrum. An input femtosecond light pulse is decomposed into a series of wavelength components. Each wavelength component with narrow spectra <1 nm width is successfully extracted into a single mode fiber. Light modulators corresponding to wavelength components are assigned to the 1st bit, the 2nd bit, the 3rd bit, , the nth bit, respectively. All of the encoded wavelength components are again recombined into a single time-varying signal and transmitted through an optical fiber. Decoding at receiving site is made by the reverse operation. Encoding and decoding for 2-bit and 4-bit signals were demonstrated for 200 fs input light pulse with about 40 nm spectral width.

We present distributed load balancing mechanisms implemented on multiprocessor systems for real time video encoding, which dynamically equalize load amounts among PE's to cope with extensive computing requirements. The loosely coupled multiprocessor system, e.g. a torus connected one, is treated as the objective system. Two decentralized controlled load balancicg algorithms are proposed, and mathematical analyses are provided to obtain some insights of our decentralized controlled mechanisms. We also prove the proposed algorithms are steady and effective theoretically and experimentally.

This paper proposes a compiler generation method for PEAS-III (Practical Environment for ASIP development), which is a configurable processor development environment for application domain specific embedded systems. Using the PEAS-III system, not only the HDL description of a target processor but also its target compiler can be generated. Therefore, execution cycles and dynamic power consumption can be rapidly evaluated. Two processors and their derivatives were designed using the PEAS-III system in the experiment. Experimental results show that the trade-offs among area, performance and power consumption of processors were analyzed in about twelve hours and the optimal processor was selected under the design constraints by using generated compilers and processors.

This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.

This paper introduces the new application specific architecture RHINE (Reconfigurable Hierarchical Image Neo-multiprocessor Engine) that is a multiprocessor system for moving picture CODEC. The array processor is known to be originally suited for data parallel processing such as image signal processing which requires vast amount of computations and has the identical instruction sequences on data. However, the moving picture CODEC algorithm suffers from the large load imbalance in the processings on multi-processors with the separated sub-images. Some load balancing techniques are indispensable in such applications for the highest speed-up. RHINE gives one of the optimal solutions for such a load balancing due to its feature of the self reconfigurable architecture. RHINE consists of Block Processing Units (BPU) hierarchically, in each of which has a common bus architecture of multiprocessors with a block memory. Processors in a BPU move to the other BPU according to the load imbalance between BPUs by switching the bus connection between BPUs. The advantage of RHINE architecture is demonstrated by showing performance simulations for real moving pictures.

In this letter, we introduce a novel patch sampling strategy for the task of image classification, which is fundamentally different from current patch sampling strategies. A top-down guidance learned from training images is used to guide patch sampling towards informative regions. Experiment results show that this approach achieved noticeable improvement over baseline patch sampling strategies for the classification of both object categories and scene categories.

Heart disease is one of the major causes of death in many advanced countries. For prevention or treatment of heart disease, getting an early diagnosis from a long time period of electrocardiogram (ECG) examination is necessary. However, it could be a large burden on medical experts to analyze this large amount of data. To reduce the burden and support the analysis, this paper proposes an arrhythmia detection method based on a deformable part model, which absorbs individual variation of ECG waveform and enables the detection of various arrhythmias. Moreover, to detect the arrhythmia in low processing delay, the proposed method only utilizes time domain features. In an experimental result, the proposed method achieved 0.91 F-measure for arrhythmia detection.

We propose a new multi-objective genetic programming (MOGP) for automatic construction of image feature extraction programs (FEPs). The proposed method was originated from a well known multi-objective evolutionary algorithm (MOEA), i.e., NSGA-II. The key differences are that redundancy-regulation mechanisms are applied in three main processes of the MOGP, i.e., population truncation, sampling, and offspring generation, to improve population diversity as well as convergence rate. Experimental results indicate that the proposed MOGP-based FEP construction system outperforms the two conventional MOEAs (i.e., NSGA-II and SPEA2) for a test problem. Moreover, we compared the programs constructed by the proposed MOGP with four human-designed object recognition programs. The results show that the constructed programs are better than two human-designed methods and are comparable with the other two human-designed methods for the test problem.

This paper proposes an efficient architecture for fractal image coding processors. The proposed architecture achieves high-speed image coding comparable to conventional JPEG processing. This architecture achieves less than 33.3 msec fractal image compression coding against a 512 512 pixel image and enables full-motion fractal image coding. The circuit size of the proposed architecture design is comparable to those of JPEG processors and much smaller than those of previously proposed fractal processors.

Bag of visual words is a promising approach to object categorization. However, in this framework, ambiguity exists in patch encoding by visual words, due to information loss caused by vector quantization. In this paper, we propose to incorporate patch-level contextual information into bag of visual words for reducing the ambiguity mentioned above. To achieve this goal, we construct a hierarchical codebook in which visual words in the upper hierarchy contain contextual information of visual words in the lower hierarchy. In the proposed method, from each sample point we extract patches of different scales, all of which are described by the SIFT descriptor. Then, we build the hierarchical codebook in which visual words created from coarse scale patches are put in the upper hierarchy, while visual words created from fine scale patches are put in the lower hierarchy. At the same time, by employing the corresponding relationship among these extracted patches, visual words in different hierarchies are associated with each other. After that, we design a method to assign patch pairs, whose patches are extracted from the same sample point, to the constructed codebook. Furthermore, to utilize image information effectively, we implement the proposed method based on two sets of features which are extracted through different sampling strategies and fuse them using a probabilistic approach. Finally, we evaluate the proposed method on dataset Caltech 101 and dataset Caltech 256. Experimental results demonstrate the effectiveness of the proposed method.

This paper studies a method for a parallel implementation of digital half toning technique, which converts continuous tone images into monotone one without losing fidelity of images. A new modified algorithm for half toning is proposed, which is able to be implemented on a rectangular or one dimensional parallel multi-processor array as a part of extensions of space partitioning image processings. The purpose of this paper is primarily to apply space partitioning local image processing technique to nonlinear recursive algorithms. The target is to achieve a fast half toning with high quality. For that propose, local directional error diffusion techniques will be introduced, which enable original recursive error diffusion half toning to be converted into a local processing algorithm without losing its original advantages of producing high quality images. The characteristics of proposed methods will be analyzed and the advantages of our algorithm of high speed processing and high quality will be demonstrated by showing the results of simulations for typical examples.

The extened Kalman filter (EKF) and unscented Kalman filter (UKF) have been successively applied in particle filter framework to generate proposal distributions, and shown significantly improving performance of the generic particle filter that uses transition prior, i.e., the system state transition prior distribution, as the proposal distribution. In this paper we propose to use the Gauss-Newton EKF/UKF to replace EKF/UKF for generating proposal distribution in a particle filter. The Gauss-Newton EKF/UKF that uses iterated measurement update can approximate the optimal proposal distribution more closer than EKF/UKF, especially in the case of significant nonlinearity in the measurement function. As a result, the Gauss-Newton EKF/UKF is able to generate and propagate the proposal distribution for each particle much better than EKF/UKF, thus further improving the performance of state estimation. Simulation results for a nonlinear/non-Gaussian time-series demonstrate the superior estimation accuracy of our method compared with state-of-the-art filters.

SIMD instructions are often implemented in modern multimedia oriented processors. Although SIMD instructions are useful for many digital signal processing applications, most compilers do not exploit SIMD instructions. The difficulty in the utilization of SIMD instructions stems from data parallelism in registers. In assembly code generation, the positions of data in registers must be noted. A technique of generating pack instructions which pack or reorder data in registers is essential for exploitation of SIMD instructions. This paper presents a code generation technique for SIMD instructions with pack instructions. SIMD instructions are generated by finding and grouping the same operations in programs. After the SIMD instruction generation, pack instructions are generated. In the pack instruction generation, Multi-valued Decision Diagram (MDD) is introduced to represent and to manipulate sets of packed data. Experimental results show that the proposed code generation technique can generate assembly code with SIMD and pack instructions performing repacking of 8 packed data in registers for a RISC processor with a dual-issue coprocessor which supports SIMD and pack instructions. The proposed method achieved speedup ratio up to about 8.5 by SIMD instructions and multiple-issue mechanism of the target processor.

Forward error correction (FEC) is one of important and heavy tasks for wireless communication. Leading edge mobile embedded systems usually support not only one FEC standard, but multiple FEC standards in order to adapt to various wireless communication standards. In this paper, we propose two-stage configurable decoder model (2-Stage CDM) for multiple FEC standards for Viterbi and Turbo coding which have a variation under the constraint length, coding rate, etc. Proposed decoder model realizes a decoder instance which supports dedicated multiple FEC standards, and rapid design for domain specific decoder is realized. Proposed decoder model is configurable in two stages: at hardware generation time and at runtime, and designers can easily specify these specifications by various design parameters. Experimental results show proposed two-stage configurable decoder model supports various domain specific FEC decoder including existing decoder, and the decoder instances based on proposed 2-Stage CDM have sufficient throughput for each communication standard and reasonable area overhead compared with existing decoder.

The heart rate variability (HRV) is a measure based on the time position of the electrocardiogram (ECG) R-waves. There is a discussion whether or not we can obtain the HRV pattern from blood pressure (BP). In this paper, we propose a method for estimating HRV from a BP signal based on a HIF algorithm and carrying out experiments to compare BP as an alternative measurement of ECG to calculate HRV. Based on the hypotheses that ECG and BP have the same harmonic behavior, we model an alternative HRV signal using a nonlinear algorithm, called heart instantaneous frequency (HIF). It tracks the instantaneous frequency through a rough fundamental frequency using power spectral density (PSD). A novelty in this work is to use fundamental frequency instead of wave-peaks as a parameter to estimate and quantify beat-to-beat heart rate variability from BP waveforms. To verify how the estimate HRV signals derived from BP using HIF correlates to the standard gold measures, i.e. HRV derived from ECG, we use a traditional algorithm based on QRS detectors followed by thresholding to localize the R-wave time peak. The results show the following: 1) The spectral error caused by misestimation of time by R-peak detectors is demonstrated by an increase in high-frequency bands followed by the loss of time domain pattern. 2) The HIF was shown to be robust against noise and nuisances. 3) By using statistical methods and nonlinear analysis no difference between HIF derived from BP and HRV derived from ECG was observed.

To measure the detrusor pressure for diagnosing lower urinary tract symptoms, we designed a small-area and low-power System on a Chip (SoC). The SoC should be small and low power because it is encapsulated in tiny air-tight capsules which are simultaneously inserted in the urinary bladder and rectum for several days. Since the SoC is also required to be programmable, we designed an Application Specific Instruction set Processor (ASIP) for pressure measurement and wireless communication, and implemented almost required functions on the ASIP. The SoC was fabricated using a 0.18 µm CMOS mixed-signal process and the chip size is 2.5 2.5 mm2. Evaluation results show that the power consumption of the SoC is 93.5 µW, and that it can operate the capsule for seven days with a tiny battery.