For formulating Quadratic Knapsack Problems (QKPs) into the form of Quadratic Unconstrained Binary Optimization (QUBO), it is necessary to introduce an integer variable, which converts and incorporates the knapsack capacity constraint into the overall energy function. In QUBO, this integer variable is encoded with auxiliary binary variables, and the encoding method used for it affects the behavior of Simulated Annealing (SA) significantly. For improving the efficiency of SA for QKP instances, this paper first visualized and analyzed their annealing processes encoded by conventional binary and unary encoding methods. Based on this analysis, we proposed a novel hybrid encoding (HE), getting the best of both worlds. The proposed HE obtained feasible solutions in the evaluation, outperforming the others in small- and medium-scale models.

A phase locking value (PLV) in electrocorticography is an essential indicator for analysis of cognitive activities and detection of severe diseases such as seizure of epilepsy. The PLV computation requires a simultaneous pursuit of high-throughput and low-cost implementation in hardware acceleration. The PLV computation consists of bandpass filtering, Hilbert transform, and mean phase coherence (MPC) calculation. The MPC calculation includes trigonometric functions and divisions, and these calculations require a lot of computational amounts. This paper proposes an MPC calculation method that removes high-cost operations from the original MPC with mathematically identical derivations while the conventional methods sacrifice either computational accuracy or throughput. This paper also proposes a hardware implementation of MPC calculator whose latency is 21 cycles and pipeline interval is five cycles. Compared with the conventional implementation with the same standard cell library, the proposed implementation marks 2.8 times better hardware implementation efficiency that is defined as throughput per gate counts.

A significant portion of computational resources of embedded systems for visual detection is dedicated to feature extraction, and this severely affects the detection accuracy and processing performance of the system. To solve this problem, we propose a feature descriptor based on histograms of oriented gradients (HOG) consisting of simple linear algebra that can extract equivalent information to the conventional HOG feature descriptor at a low computational cost. In an evaluation, a leading-edge detection algorithm with this decomposed vector HOG (DV-HOG) achieved equivalent or better detection accuracy compared with conventional HOG feature descriptors. A hardware implementation of DV-HOG occupies approximately 14.2 times smaller cell area than that of a conventional HOG implementation.

Annealing computation has recently attracted attention as it can efficiently solve combinatorial optimization problems using an Ising spin-glass model. Stochastic cellular automata annealing (SCA) is a promising algorithm that can realize fast spin-update by utilizing its parallel computing capability. However, in SCA, pinning effect control to suppress the spin-flip probability is essential, making escaping from local minima more difficult than serial spin-update algorithms, depending on the problem. This paper proposes a novel approach called APC-SCA (Autonomous Pinning effect Control SCA), where the pinning effect can be controlled autonomously by focusing on individual spin-flip. The evaluation results using max-cut, N-queen, and traveling salesman problems demonstrate that APC-SCA can obtain better solutions than the original SCA that uses pinning effect control pre-optimized by a grid search. Especially in solving traveling salesman problems, we confirm that the tour distance obtained by APC-SCA is up to 56.3% closer to the best-known compared to the conventional approach.

Heart disease is one of the major causes of death in many advanced countries. For prevention or treatment of heart disease, getting an early diagnosis from a long time period of electrocardiogram (ECG) examination is necessary. However, it could be a large burden on medical experts to analyze this large amount of data. To reduce the burden and support the analysis, this paper proposes an arrhythmia detection method based on a deformable part model, which absorbs individual variation of ECG waveform and enables the detection of various arrhythmias. Moreover, to detect the arrhythmia in low processing delay, the proposed method only utilizes time domain features. In an experimental result, the proposed method achieved 0.91 F-measure for arrhythmia detection.

Visual object detection on embedded systems involves a multi-objective optimization problem in the presence of trade-offs between power consumption, processing performance, and detection accuracy. For a new Pareto solution with high processing performance and low power consumption, this paper proposes a hardware architecture for decision tree ensemble using multiple channels of features. For efficient detection, the proposed architecture utilizes the dimensionality of feature channels in addition to parallelism in image space and adopts task scheduling to attain random memory access without conflict. Evaluation results show that an FPGA implementation of the proposed architecture with an aggregated channel features pedestrian detector can process 229 million samples per second at 100MHz operation frequency while it requires a relatively small amount of resources. Consequently, the proposed architecture achieves 350fps processing performance for 1080P Full HD images and outperforms conventional object detection hardware architectures developed for embedded systems.