Visual object detection on embedded systems involves a multi-objective optimization problem in the presence of trade-offs between power consumption, processing performance, and detection accuracy. For a new Pareto solution with high processing performance and low power consumption, this paper proposes a hardware architecture for decision tree ensemble using multiple channels of features. For efficient detection, the proposed architecture utilizes the dimensionality of feature channels in addition to parallelism in image space and adopts task scheduling to attain random memory access without conflict. Evaluation results show that an FPGA implementation of the proposed architecture with an aggregated channel features pedestrian detector can process 229 million samples per second at 100MHz operation frequency while it requires a relatively small amount of resources. Consequently, the proposed architecture achieves 350fps processing performance for 1080P Full HD images and outperforms conventional object detection hardware architectures developed for embedded systems.

A significant portion of computational resources of embedded systems for visual detection is dedicated to feature extraction, and this severely affects the detection accuracy and processing performance of the system. To solve this problem, we propose a feature descriptor based on histograms of oriented gradients (HOG) consisting of simple linear algebra that can extract equivalent information to the conventional HOG feature descriptor at a low computational cost. In an evaluation, a leading-edge detection algorithm with this decomposed vector HOG (DV-HOG) achieved equivalent or better detection accuracy compared with conventional HOG feature descriptors. A hardware implementation of DV-HOG occupies approximately 14.2 times smaller cell area than that of a conventional HOG implementation.