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Phase Locking Value Calculator Based on Hardware-Oriented Mathematical Expression

Tomoki SUGIURA, Jaehoon YU, Yoshinori TAKEUCHI

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Summary :

A phase locking value (PLV) in electrocorticography is an essential indicator for analysis of cognitive activities and detection of severe diseases such as seizure of epilepsy. The PLV computation requires a simultaneous pursuit of high-throughput and low-cost implementation in hardware acceleration. The PLV computation consists of bandpass filtering, Hilbert transform, and mean phase coherence (MPC) calculation. The MPC calculation includes trigonometric functions and divisions, and these calculations require a lot of computational amounts. This paper proposes an MPC calculation method that removes high-cost operations from the original MPC with mathematically identical derivations while the conventional methods sacrifice either computational accuracy or throughput. This paper also proposes a hardware implementation of MPC calculator whose latency is 21 cycles and pipeline interval is five cycles. Compared with the conventional implementation with the same standard cell library, the proposed implementation marks 2.8 times better hardware implementation efficiency that is defined as throughput per gate counts.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E101-A No.12 pp.2254-2261
Publication Date
2018/12/01
Publicized
Online ISSN
1745-1337
DOI
10.1587/transfun.E101.A.2254
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category

Authors

Tomoki SUGIURA
  the Graduate School of Osaka University
Jaehoon YU
  the Graduate School of Osaka University
Yoshinori TAKEUCHI
  the Graduate School of Osaka University

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