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A phase locking value (PLV) in electrocorticography is an essential indicator for analysis of cognitive activities and detection of severe diseases such as seizure of epilepsy. The PLV computation requires a simultaneous pursuit of high-throughput and low-cost implementation in hardware acceleration. The PLV computation consists of bandpass filtering, Hilbert transform, and mean phase coherence (MPC) calculation. The MPC calculation includes trigonometric functions and divisions, and these calculations require a lot of computational amounts. This paper proposes an MPC calculation method that removes high-cost operations from the original MPC with mathematically identical derivations while the conventional methods sacrifice either computational accuracy or throughput. This paper also proposes a hardware implementation of MPC calculator whose latency is 21 cycles and pipeline interval is five cycles. Compared with the conventional implementation with the same standard cell library, the proposed implementation marks 2.8 times better hardware implementation efficiency that is defined as throughput per gate counts.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E101-A No.12 pp.2254-2261

- Publication Date
- 2018/12/01

- Publicized

- Online ISSN
- 1745-1337

- DOI
- 10.1587/transfun.E101.A.2254

- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)

- Category

Tomoki SUGIURA

the Graduate School of Osaka University

Jaehoon YU

the Graduate School of Osaka University

Yoshinori TAKEUCHI

the Graduate School of Osaka University

The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.

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Tomoki SUGIURA, Jaehoon YU, Yoshinori TAKEUCHI, "Phase Locking Value Calculator Based on Hardware-Oriented Mathematical Expression" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 12, pp. 2254-2261, December 2018, doi: 10.1587/transfun.E101.A.2254.

Abstract: A phase locking value (PLV) in electrocorticography is an essential indicator for analysis of cognitive activities and detection of severe diseases such as seizure of epilepsy. The PLV computation requires a simultaneous pursuit of high-throughput and low-cost implementation in hardware acceleration. The PLV computation consists of bandpass filtering, Hilbert transform, and mean phase coherence (MPC) calculation. The MPC calculation includes trigonometric functions and divisions, and these calculations require a lot of computational amounts. This paper proposes an MPC calculation method that removes high-cost operations from the original MPC with mathematically identical derivations while the conventional methods sacrifice either computational accuracy or throughput. This paper also proposes a hardware implementation of MPC calculator whose latency is 21 cycles and pipeline interval is five cycles. Compared with the conventional implementation with the same standard cell library, the proposed implementation marks 2.8 times better hardware implementation efficiency that is defined as throughput per gate counts.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.2254/_p

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@ARTICLE{e101-a_12_2254,

author={Tomoki SUGIURA, Jaehoon YU, Yoshinori TAKEUCHI, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={Phase Locking Value Calculator Based on Hardware-Oriented Mathematical Expression},

year={2018},

volume={E101-A},

number={12},

pages={2254-2261},

abstract={A phase locking value (PLV) in electrocorticography is an essential indicator for analysis of cognitive activities and detection of severe diseases such as seizure of epilepsy. The PLV computation requires a simultaneous pursuit of high-throughput and low-cost implementation in hardware acceleration. The PLV computation consists of bandpass filtering, Hilbert transform, and mean phase coherence (MPC) calculation. The MPC calculation includes trigonometric functions and divisions, and these calculations require a lot of computational amounts. This paper proposes an MPC calculation method that removes high-cost operations from the original MPC with mathematically identical derivations while the conventional methods sacrifice either computational accuracy or throughput. This paper also proposes a hardware implementation of MPC calculator whose latency is 21 cycles and pipeline interval is five cycles. Compared with the conventional implementation with the same standard cell library, the proposed implementation marks 2.8 times better hardware implementation efficiency that is defined as throughput per gate counts.},

keywords={},

doi={10.1587/transfun.E101.A.2254},

ISSN={1745-1337},

month={December},}

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TY - JOUR

TI - Phase Locking Value Calculator Based on Hardware-Oriented Mathematical Expression

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 2254

EP - 2261

AU - Tomoki SUGIURA

AU - Jaehoon YU

AU - Yoshinori TAKEUCHI

PY - 2018

DO - 10.1587/transfun.E101.A.2254

JO - IEICE TRANSACTIONS on Fundamentals

SN - 1745-1337

VL - E101-A

IS - 12

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - December 2018

AB - A phase locking value (PLV) in electrocorticography is an essential indicator for analysis of cognitive activities and detection of severe diseases such as seizure of epilepsy. The PLV computation requires a simultaneous pursuit of high-throughput and low-cost implementation in hardware acceleration. The PLV computation consists of bandpass filtering, Hilbert transform, and mean phase coherence (MPC) calculation. The MPC calculation includes trigonometric functions and divisions, and these calculations require a lot of computational amounts. This paper proposes an MPC calculation method that removes high-cost operations from the original MPC with mathematically identical derivations while the conventional methods sacrifice either computational accuracy or throughput. This paper also proposes a hardware implementation of MPC calculator whose latency is 21 cycles and pipeline interval is five cycles. Compared with the conventional implementation with the same standard cell library, the proposed implementation marks 2.8 times better hardware implementation efficiency that is defined as throughput per gate counts.

ER -