IEICE TRANSACTIONS on Fundamentals
Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design
Summary :
Forward error correction (FEC) is one of important and heavy tasks for wireless communication. Leading edge mobile embedded systems usually support not only one FEC standard, but multiple FEC standards in order to adapt to various wireless communication standards. In this paper, we propose two-stage configurable decoder model (2-Stage CDM) for multiple FEC standards for Viterbi and Turbo coding which have a variation under the constraint length, coding rate, etc. Proposed decoder model realizes a decoder instance which supports dedicated multiple FEC standards, and rapid design for domain specific decoder is realized. Proposed decoder model is configurable in two stages: at hardware generation time and at runtime, and designers can easily specify these specifications by various design parameters. Experimental results show proposed two-stage configurable decoder model supports various domain specific FEC decoder including existing decoder, and the decoder instances based on proposed 2-Stage CDM have sufficient throughput for each communication standard and reasonable area overhead compared with existing decoder.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.12 pp.2659-2668
- Publication Date
- 2011/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.2659
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- High-Level Synthesis and System-Level Design
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Keyword
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Ittetsu TANIGUCHI, Ayataka KOBAYASHI, Keishi SAKANUSHI, Yoshinori TAKEUCHI, Masaharu IMAI, "Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 12, pp. 2659-2668, December 2011, doi: 10.1587/transfun.E94.A.2659.
Abstract: Forward error correction (FEC) is one of important and heavy tasks for wireless communication. Leading edge mobile embedded systems usually support not only one FEC standard, but multiple FEC standards in order to adapt to various wireless communication standards. In this paper, we propose two-stage configurable decoder model (2-Stage CDM) for multiple FEC standards for Viterbi and Turbo coding which have a variation under the constraint length, coding rate, etc. Proposed decoder model realizes a decoder instance which supports dedicated multiple FEC standards, and rapid design for domain specific decoder is realized. Proposed decoder model is configurable in two stages: at hardware generation time and at runtime, and designers can easily specify these specifications by various design parameters. Experimental results show proposed two-stage configurable decoder model supports various domain specific FEC decoder including existing decoder, and the decoder instances based on proposed 2-Stage CDM have sufficient throughput for each communication standard and reasonable area overhead compared with existing decoder.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.2659/_p
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@ARTICLE{e94-a_12_2659,
author={Ittetsu TANIGUCHI, Ayataka KOBAYASHI, Keishi SAKANUSHI, Yoshinori TAKEUCHI, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design},
year={2011},
volume={E94-A},
number={12},
pages={2659-2668},
abstract={Forward error correction (FEC) is one of important and heavy tasks for wireless communication. Leading edge mobile embedded systems usually support not only one FEC standard, but multiple FEC standards in order to adapt to various wireless communication standards. In this paper, we propose two-stage configurable decoder model (2-Stage CDM) for multiple FEC standards for Viterbi and Turbo coding which have a variation under the constraint length, coding rate, etc. Proposed decoder model realizes a decoder instance which supports dedicated multiple FEC standards, and rapid design for domain specific decoder is realized. Proposed decoder model is configurable in two stages: at hardware generation time and at runtime, and designers can easily specify these specifications by various design parameters. Experimental results show proposed two-stage configurable decoder model supports various domain specific FEC decoder including existing decoder, and the decoder instances based on proposed 2-Stage CDM have sufficient throughput for each communication standard and reasonable area overhead compared with existing decoder.},
keywords={},
doi={10.1587/transfun.E94.A.2659},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2659
EP - 2668
AU - Ittetsu TANIGUCHI
AU - Ayataka KOBAYASHI
AU - Keishi SAKANUSHI
AU - Yoshinori TAKEUCHI
AU - Masaharu IMAI
PY - 2011
DO - 10.1587/transfun.E94.A.2659
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2011
AB - Forward error correction (FEC) is one of important and heavy tasks for wireless communication. Leading edge mobile embedded systems usually support not only one FEC standard, but multiple FEC standards in order to adapt to various wireless communication standards. In this paper, we propose two-stage configurable decoder model (2-Stage CDM) for multiple FEC standards for Viterbi and Turbo coding which have a variation under the constraint length, coding rate, etc. Proposed decoder model realizes a decoder instance which supports dedicated multiple FEC standards, and rapid design for domain specific decoder is realized. Proposed decoder model is configurable in two stages: at hardware generation time and at runtime, and designers can easily specify these specifications by various design parameters. Experimental results show proposed two-stage configurable decoder model supports various domain specific FEC decoder including existing decoder, and the decoder instances based on proposed 2-Stage CDM have sufficient throughput for each communication standard and reasonable area overhead compared with existing decoder.
ER -
English
