IEICE TRANSACTIONS on Fundamentals
A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency
Summary :
This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.11 pp.2356-2365
- Publication Date
- 1999/11/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
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Katsuya SHINOHARA, Norimasa OHTSUKI, Yoshinori TAKEUCHI, Masaharu IMAI, "A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 11, pp. 2356-2365, November 1999, doi: .
Abstract: This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_11_2356/_p
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@ARTICLE{e82-a_11_2356,
author={Katsuya SHINOHARA, Norimasa OHTSUKI, Yoshinori TAKEUCHI, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency},
year={1999},
volume={E82-A},
number={11},
pages={2356-2365},
abstract={This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Performance Optimization Method for Pipelined ASIPs in Consideration of Clock Frequency
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2356
EP - 2365
AU - Katsuya SHINOHARA
AU - Norimasa OHTSUKI
AU - Yoshinori TAKEUCHI
AU - Masaharu IMAI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 11
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - November 1999
AB - This paper proposes an ASIP performance optimization method taking clock frequency into account. The performance of an instruction set processor can be measured using the execution time of an application program, which can be determined by the clock cycles to perform the application program divided by the applied clock frequency. Therefore, the clock frequency should also be tuned in order to maximize the performance of the processor under the given design constraints. Experimental results show that the proposed method determines an optimal combination of FUs considering clock frequency.
ER -
English
