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A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors

Shinsuke KOBAYASHI, Kentaro MITA, Yoshinori TAKEUCHI, Masaharu IMAI

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Summary :

This paper proposes a compiler generation method for PEAS-III (Practical Environment for ASIP development), which is a configurable processor development environment for application domain specific embedded systems. Using the PEAS-III system, not only the HDL description of a target processor but also its target compiler can be generated. Therefore, execution cycles and dynamic power consumption can be rapidly evaluated. Two processors and their derivatives were designed using the PEAS-III system in the experiment. Experimental results show that the trade-offs among area, performance and power consumption of processors were analyzed in about twelve hours and the optimal processor was selected under the design constraints by using generated compilers and processors.

Publication
IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2586-2595
Publication Date
2002/12/01
Publicized
Online ISSN
DOI
Type of Manuscript
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category
Hardware/Software Codesign

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