IEICE TRANSACTIONS on Fundamentals
A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors
Summary :
This paper proposes a compiler generation method for PEAS-III (Practical Environment for ASIP development), which is a configurable processor development environment for application domain specific embedded systems. Using the PEAS-III system, not only the HDL description of a target processor but also its target compiler can be generated. Therefore, execution cycles and dynamic power consumption can be rapidly evaluated. Two processors and their derivatives were designed using the PEAS-III system in the experiment. Experimental results show that the trade-offs among area, performance and power consumption of processors were analyzed in about twelve hours and the optimal processor was selected under the design constraints by using generated compilers and processors.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.12 pp.2586-2595
- Publication Date
- 2002/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Hardware/Software Codesign
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Shinsuke KOBAYASHI, Kentaro MITA, Yoshinori TAKEUCHI, Masaharu IMAI, "A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 12, pp. 2586-2595, December 2002, doi: .
Abstract: This paper proposes a compiler generation method for PEAS-III (Practical Environment for ASIP development), which is a configurable processor development environment for application domain specific embedded systems. Using the PEAS-III system, not only the HDL description of a target processor but also its target compiler can be generated. Therefore, execution cycles and dynamic power consumption can be rapidly evaluated. Two processors and their derivatives were designed using the PEAS-III system in the experiment. Experimental results show that the trade-offs among area, performance and power consumption of processors were analyzed in about twelve hours and the optimal processor was selected under the design constraints by using generated compilers and processors.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_12_2586/_p
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@ARTICLE{e85-a_12_2586,
author={Shinsuke KOBAYASHI, Kentaro MITA, Yoshinori TAKEUCHI, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors},
year={2002},
volume={E85-A},
number={12},
pages={2586-2595},
abstract={This paper proposes a compiler generation method for PEAS-III (Practical Environment for ASIP development), which is a configurable processor development environment for application domain specific embedded systems. Using the PEAS-III system, not only the HDL description of a target processor but also its target compiler can be generated. Therefore, execution cycles and dynamic power consumption can be rapidly evaluated. Two processors and their derivatives were designed using the PEAS-III system in the experiment. Experimental results show that the trade-offs among area, performance and power consumption of processors were analyzed in about twelve hours and the optimal processor was selected under the design constraints by using generated compilers and processors.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - A Compiler Generation Method for HW/SW Codesign Based on Configurable Processors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2586
EP - 2595
AU - Shinsuke KOBAYASHI
AU - Kentaro MITA
AU - Yoshinori TAKEUCHI
AU - Masaharu IMAI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2002
AB - This paper proposes a compiler generation method for PEAS-III (Practical Environment for ASIP development), which is a configurable processor development environment for application domain specific embedded systems. Using the PEAS-III system, not only the HDL description of a target processor but also its target compiler can be generated. Therefore, execution cycles and dynamic power consumption can be rapidly evaluated. Two processors and their derivatives were designed using the PEAS-III system in the experiment. Experimental results show that the trade-offs among area, performance and power consumption of processors were analyzed in about twelve hours and the optimal processor was selected under the design constraints by using generated compilers and processors.
ER -
English
