IEICE TRANSACTIONS on Fundamentals
VLSI Architecture for Real-Time Fractal Image Coding Processors
Summary :
This paper proposes an efficient architecture for fractal image coding processors. The proposed architecture achieves high-speed image coding comparable to conventional JPEG processing. This architecture achieves less than 33.3 msec fractal image compression coding against a 512
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- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.3 pp.452-458
- Publication Date
- 2000/03/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa)
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Hideki YAMAUCHI, Yoshinori TAKEUCHI, Masaharu IMAI, "VLSI Architecture for Real-Time Fractal Image Coding Processors" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 3, pp. 452-458, March 2000, doi: .
Abstract: This paper proposes an efficient architecture for fractal image coding processors. The proposed architecture achieves high-speed image coding comparable to conventional JPEG processing. This architecture achieves less than 33.3 msec fractal image compression coding against a 512
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_3_452/_p
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@ARTICLE{e83-a_3_452,
author={Hideki YAMAUCHI, Yoshinori TAKEUCHI, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={VLSI Architecture for Real-Time Fractal Image Coding Processors},
year={2000},
volume={E83-A},
number={3},
pages={452-458},
abstract={This paper proposes an efficient architecture for fractal image coding processors. The proposed architecture achieves high-speed image coding comparable to conventional JPEG processing. This architecture achieves less than 33.3 msec fractal image compression coding against a 512
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - VLSI Architecture for Real-Time Fractal Image Coding Processors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 452
EP - 458
AU - Hideki YAMAUCHI
AU - Yoshinori TAKEUCHI
AU - Masaharu IMAI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2000
AB - This paper proposes an efficient architecture for fractal image coding processors. The proposed architecture achieves high-speed image coding comparable to conventional JPEG processing. This architecture achieves less than 33.3 msec fractal image compression coding against a 512
ER -
English
