A synthesizable HDL generation method for pipelined processors is proposed. By using the proposed method, data-path and control logic descriptions of a target processor is generated from a clock based instruction set specification. From the experimental results, feasibility of the proposed method is evaluated and the amount of processor design time was drastically reduced than that of conventional RT level manual design in HDL.

We have already proposed a process algebra µLOTOS as a mathematical framework to synthesize a process from a number of (incomplete) specifications, in which requirements for the process do not have to be completely determined. It is guaranteed that the synthesized process satisfies all the given specifications, if they are consistent. For example, µLOTOS is useful for incremental design. The advantage of µLOTOS is that liveness properties can be expressed by least fixpoints and disjunctions . In this paper, we present µLOTOS^R, which is a refined µLOTOS. The improvement is that µLOTOS^R has a conjunction operator . Therefore, the consistency between a number of specifications S₁,,S₂ can be checked by the satisfiability of the conjunction specification S₁ S₂. µLOTOS^R does not need the complex consistency check used in µLOTOS.

This paper presents a new technique for accurately modeling uni-directional High-Voltage lightly-doped- drain MOS (HV MOS) devices by extending the bi- directional HV MOS model and adopting a new parameter extraction method. We have already reported on a SPICE model for bi-directional HV MOS devices based on BSIM3v3. However, if we apply this bi- directional HV MOS model and its parameter extraction technique directly to uni-directional HV MOS devices, there are large discrepancies between the measured and simulated I-V characteristics of the uni- directional devices. This paper extends the bi- directional HV MOS model, and adopts a new parameter extraction technique. Using parameters extracted with the new method, the simulated I-V characteristics of the uni-directional n-channel HV MOS device match the measured results well. Since our method does not change any model equations of BSIM3v3, it can be applied to any SPICE simulator on which the BSIM3v3 model runs.

In the phase locked loop (PLL) frequency synthesizer which is used in a higher frequency region, the prescaler method is employed in order to increase the operating frequency of the programmable divider. However, since the fixed divider whose division ratio is same as the prescaler is installed at the following stage of the reference divider, the reference frequency is decreased and the performance of the PLL frequency synthesizer is degraded. The prescaler PLL frequency synthesizer using multi-programmable divider is one of the counter measures answering the request. In this paper we propose the reduction of the number of programmable dividers by using the (N+1/2) programmable divider. The effectiveness of the proposed method is confirmed by experimental results.

In a phase-locked-loop (PLL) frequency synthesizer with binary phase comparison, jitter is hard to suppress. In this paper, we propose a PLL frequency synthesizer with an improved binary phase comparison which can solve the above problem. The effectiveness of the proposed method is confirmed by PSpice simulation results.

This paper presents the switching control and VLSI architecture for the AAL2 switch. The ATM network with the AAL2 switch can efficiently transmit low-bit-rate data, even if the network has many endpoints. The switch is capable of not only switching AAL2 cells but also converting the header of other types of ATMs. The AAL2 switch is integrated into a single chip. The proposed ATM network is constructed by AAL2 switches attached to the ATM switches.

In digital signal processing, bit width of intermediate variables should be longer than that of input and output variables in order to execute intermediate operations with high precision. Then a processor core for digital signal processing is required to have two types of register files, one of which is used by input and output variables and the other one is used by intermediate variables. This paper proposes a hardware/software cosynthesis system for digital signal processor cores with two types of register files. Given an application program and its data, the system synthesizes a hardware description of a processor core, an object code running on the processor core, and software environments. A synthesized processor core can be composed of a processor kernel, multiple data memory buses, hardware loop units, addressing units, and multiple functional units. Furthermore it can have two types of register files RF₁ and RF₂. The bit width and number of registers in RF₁ or RF₂ will be determined based on a given application program. Thus a synthesized processor core will have small area with keeping high precision of intermediate operations compared with a processor core with only one register file. The experimental results demonstrate the effectiveness of the proposed system.

This paper proposes an efficient architecture for fractal image coding processors. The proposed architecture achieves high-speed image coding comparable to conventional JPEG processing. This architecture achieves less than 33.3 msec fractal image compression coding against a 512 512 pixel image and enables full-motion fractal image coding. The circuit size of the proposed architecture design is comparable to those of JPEG processors and much smaller than those of previously proposed fractal processors.

Graph products have important role in constructing many useful networks. It is known that there are four basic graph products. Properties of each product have been studied individually. We propose a unified approach to these products based on the distance in graphs, and new two products on graphs. The viewpoint of products based on the distance introduced here provides a family of products that includes almost known graph products as extremal ones and suggests new products. Also,we study relations among these six products. Finally, we investigate several classes of graph products in those context.

System level diagnosis that can identify the faulty units in the system was introduced by Preparata, Metze, and Chien. In this area, the fundamental problem is to decide the diagnosability of given networks. We study the diagnosability of networks represented by the cartesian product. Our result is the optimal one with respect to the restriction of degrees of vertices of graphs that represent the networks.

This paper deals with two-processor scheduling for general acyclic SWITCH-less program nets with random node firing times. First, we introduce a hybrid priority list L^* that has been shown to generate optimal schedules for the acyclic SWITCH-less program nets with unity node firing times, of which AND-nodes possess at most single input edge. Then considering the factors of existence of the AND-nodes with two input edges as well as random node firing times, we extend L^* to design a new dynamic priority list L_d and four static priority lists {L_sii=1,2,3,4}; and then combining L_d and L_si (i=1,2,3,4) we propose four hybrid priority lists {L^*_ii=1,2,3,4}. Finally, we apply genetic algorithm to evaluate the schedules generated by the four lists through simulations on 400 program nets. Our simulation results show two of the four lists can generate reasonably good schedules.

The legal firing sequence problem (LFS) asks if it is possible to fire each transition some prescribed number of times in a given Petri net. It is a fundamental problem in Petri net theory as it appears as a subproblem, or as a simplified version of marking reachability, minimum initial resource allocation, liveness, and some scheduling problems. It is also known to be NP-hard, however, even under various restrictions on nets (and on firing counts), and no efficient algorithm has been previously reported for any class of nets having general edge weights. We show in this paper that LFS can be solved in polynomial time (in O(n log n) time) for a subclass of state machines, called cacti, with arbitrary edge weights allowed (if each transition is asked to be fired exactly once).

This paper discusses a method of designing linear phase two-channel filter banks for integer wavelet transform. We show that the designed filter banks are easily structed as the lifting form by leading relationship between designed filters and lifting structure. The designed integer wavelets are applied to image compression to verify the efficiency of our method.

In this paper, a puzzle called Cell-Maze is analyzed. In this puzzle, cells are arranged in checker board squares. Each cell is rotated when a player arrives at the cell. Cell-Maze asks whether or not a player started from a start cell can reach a goal cell. The reachability problem for ordinary graphs can be easily solved in linear time, however a reachability problem for the network such as Cell-Maze may be extremely difficult. In this paper, NP-hardness of this puzzle is proved. It is proved by reducing Hamiltonian Circuit Problem of directed planar graph G such that each vertex involved in just three arcs. Furthermore, we consider subproblems, which can be solved in polynomial time.

A nonlinear multiple complex sinusoidal estimator (NMSE) is proposed, as an extended and improved version with system noise of the single sinusoidal estimator previously presented by the author, for extracting multiple complex sinusoids in white noise. This estimator is derived by applying an extended complex Kalman filter (ECKF) to a noisy multiple complex sinusoidal model with state-representation, where the model becomes a nonlinear stochastic system. Proof of the stability is given by using a structure of the state-space signal model and Lyapunov techniques. Also, computer simulations demonstrate the effectiveness of the NMSE from various points of view.

It is an important problem in signal processing, system realization and system identification to find linear discrete-time systems which are consistent with given covariance parameters. This problem is formulated as a problem of finding discrete-time positive real functions which interpolate given covariance parameters. Among various solutions to the problem, a recent remarkable one is a parameterization of all the discrete-time strictly positive real functions that interpolate the covariance parameters and have a limited McMillan degree. In this paper, we use more general input-output characteristics than covariance parameters and consider finding discrete-time positive real functions which interpolate such characteristics. The input-output characteristics are given by the coefficients of the Taylor series at some complex points in the open unit disk. Based on our previous work, we present an algorithm to generate all the discrete-time positive real functions that interpolate the input-output characteristics and have a limited McMillan degree. The algorithm is more general and simpler than the previous one, and is an important practical supplement to the previous work. Moreover, the interpolation of the general input-output characteristics can be effectively applied to the frequency-weighted model reduction. Hence, the algorithm makes a contribution to the problem from the practical viewpoint as well as the theoretical viewpoint.

We study the problem of stabilizing a general nonlinear control system globally based on direct gradient descent control which is a dynamic feedback control law. The direct gradient descent control and the general nonlinear control system (original system) form a new system (extended system). Under an appropriate assumption we can make the extended system become globally asymptotically stable if its unforced system is stable in the sense of Lyapunov.

Nonlinear dynamics of x_n+1=λ {4x_n (1-x_n)}^q is studied in this paper. Different from the logistic map (q=1), in the case of q<q₁=(33-3)/12=0.22871, there exists subcritical bifurcation because the Schwarzian derivative cannot preserve its sign at the fixed point. Moreover, when q<q₂=0.17585 and λ=1.0, a stable period 1 orbit appears due to stabilization of the non-zero fixed point. Intermittent chaos due to the type 3 of intermittency is also found in this system.

Recently, digital contents are copied easily because of the development of digital technology. So digital watermark technique which aims at copyright protection of digital contents becomes more and more important, and various watermarking methods have been proposed. In this paper, we proposed a method of digital watermark for still image by using wavelet packets, and examine the robustness of the watermarking method against several image processings. This method can be easily applied to the watermark for video because in this method, embedded data are detected without original image. Therefore, we extend the wavelet-based watermarking method to the case of watermark for video.

Coding scheme for a noisy multiple-access adder channel is proposed. When a T-user δ-decodable affine code C is given a priori, a qT-user λ δ-decodable affine code C^* is produced by using a q q matrix B satisfying BA=λ I_{q q}, e. g. , a Hadamard matrix or a conference matrix. In particular, the case of δ=1 is considered for the practical purposes. A (2n-1)-user uniquely decodable (δ=1) affine code Cⁿ with arbitrary code length n is recursively constructed. When Cⁿ plays a role of C, a q(2n-1)-user λ-decodable affine code C^* is obtained. The code length and the number of users of C^* are more flexible than those of the Wilson's code. The total rate of the λ-decodable code in this paper tends to be higher than that of the λ-decodable code by Wilson as the number of users increases.

We proposed a new model for non-stationary time series analysis based on an inhomogeneous AR (autoregressive) equation. Time series data is regarded as white noise plus output of an AR system excited by non-stationary input sequence represented in terms of a set of basis. A method of model parameter estimation was presented when the set of basis and the AR order are given. In order to extend the method, we present a method of parameter estimation when the AR order is unknown: we set two new criteria 1) minimize the root mean square error of the output sequence, and 2) minimize scattering of estimated frequencies. Then, we derive a procedure for the estimation of the AR order and the other unknown parameters.

The robust induced l-norm control problem is considered for uncertain discrete-time systems. We propose a state feedback and an output feedback controller that quadratically stabilize the systems and satisfy a given constraint on the induced l-norm. Both controllers are constructed by solving a set of scalar-dependent linear matrix inequalities (LMI's), and the gain matrices are characterized by the solution to the LMI's.

In this study, a simple chaos communication system including modulation-demodulation circuits is studied. The influence of modulation-demodulation circuits to chaos synchronization is investigated. For the estimation of communication quality, bit error rate (BER) is calculated by computer simulation when a sequential random pulse information signal is transmitted via this proposed system.

In this paper, we propose a new secure server-aided RSA secret computation protocol which guards against not only the attacks in [1],[2],[15],[18] but also the new powerful active attacks in [3],[4]. The new protocol is also efficient to support high security level.

In this letter we propose a new Shape from Focus (SFF) method using piecewise curved search windows for accurate 3-D shape recovery. The new method uses piecewise curved windows to compute focus measure and to search for Focus Image Surface (FIS) in image space. The experimental result shows that our new method gives more accurate result than the previous SFF methods.

This article theoretically provides the ensemble average and the ensemble variance of membrane potential of an integrate-and-fire neuron, when the neuron receives random spikes from the other neurons. The model assumes that EPSPs rise and fall continuously. Our theoretical result shows good agreement with a numerical simulation.

Signal conservation logic (SCL) is a model of logic for the physical world subject to the matter conservation law. This letter proves that replication, complementary replication, and computational universality called elemental universality are equivalent in SCL. Since intelligence has a close relation to computational universality, the presented theorem may mean that life under the matter conservation law eventually acquires some kind of intelligence.