To guarantee strict Quality of Service (QoS) for real-time applications, we have previously proposed an output buffer control mechanism in IP routers, confirmed its effectiveness through simulations, and implemented a prototype. This mechanism can guarantee strict QoS within a single router. In this paper, we propose a control scheme of cooperation between IP routers equipped with this mechanism by using one of the signaling protocols. Our proposed scheme aims to stabilize End-to-End (E2E) flow delay within the target delay. In addition, our mechanism dynamically updates reserved resources between IP routers to improve E2E packet loss rate. We present an implemented design of our scheme and an empirical evaluation of the implementation. These results show quantitatively how our scheme improves the quality of video pictures.

This paper presents novel multimedia ATM networks which are capable of transmitting voice data efficiently and unify the switching methods among heterogeneous traffic. Fully ATMized multimedia networks are using fellow cell switches. The proposed assembly method can pack plural calls which have different virtual channel connection (VCC) into one cell. Every call in cells is able to be dynamically rearranged by the fellow cell switch to achieve an efficient use of network resources. The switching functions are supported by shared virtual channel identifier (VCI) cells and fellow cells in it. The fellow cell switch for 622 Mbps links is integrated into a single chip. The multimedia ATM networks including voice transmission can be constructed by the fellow cell switches being attached to the standard ATM switches.

This paper presents the switching control and VLSI architecture for the AAL2 switch. The ATM network with the AAL2 switch can efficiently transmit low-bit-rate data, even if the network has many endpoints. The switch is capable of not only switching AAL2 cells but also converting the header of other types of ATMs. The AAL2 switch is integrated into a single chip. The proposed ATM network is constructed by AAL2 switches attached to the ATM switches.

The design procedure of a multithreaded processor dedicated to the image generation is described, which can be achieved by means of a high-level synthesis tool PARTHENON. The processor employs a multithreaded architecture which is a novel promising approach to the parallel image generation. This paper puts special stress on the high-level synthesis scheme which can simplify the behavioral description for the structure and control of a complex hardware, and therefore enables the design of a complicated mechanism for a multithreaded processor. Implementation results of the synthesis are also shown to demonstrate the performance of the designed processor. This processor greatly improves the throughput of the image generation so far attained by the conventional approach.

A single chip MPEG2 MP@HL Video decoder has been developed, which consists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip frame memories and the interfaces associated with it. Owing to sophisticated I/O interfaces among functional units, the macroblock level pipeline in conjunction with different decording facilities attains a high throughput to such an extent as to decode HDTV images in real time. Moreover, a set of these functional units, pipeline buffers, and frame memory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8 9.2mm2 with a 0.6µm triple-mental CMOS technology, and dissipates 1.2 W from a single 3.3 V supply.

A flooding algorithm is an indispensable and fundamental network control mechanism for achieving some tasks, such notifying all nodes of some information, transferring data with high reliability, getting some information from all nodes, or to reserve a route by flooding the messages in the network. In particular, the flooding algorithm is greatly effective in the heterogeneous and dynamic network environment such as so-called ubiquitous networks, whose topology is indefinite or changes dynamically and whose nodal function may be simple and less intelligent. Actually, it is applied to grasp the network topology in a sensor network or an ad-hoc network, or to retrieve content information by mobile agent systems. A flooding algorithm has the advantages of robustness and optimality by parallel processing of messages. However, the flooding mechanism has a fundamental disadvantages: it causes the message congestion in the network, and eventually increases the processing time until the flooding control is finished. In this paper, we propose and evaluate methods for producing a more efficient flooding algorithm by adopting the growth processes of primitive creatures, such as molds or microbes.