IEICE TRANSACTIONS on Fundamentals
Single Chip Implementation of MPEG2 Decoder for HDTV Level Pictures
Summary :
A single chip MPEG2 MP@HL Video decoder has been developed, which consists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip frame memories and the interfaces associated with it. Owing to sophisticated I/O interfaces among functional units, the macroblock level pipeline in conjunction with different decording facilities attains a high throughput to such an extent as to decode HDTV images in real time. Moreover, a set of these functional units, pipeline buffers, and frame memory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E79-A No.3 pp.330-338
- Publication Date
- 1996/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section of Selected Papers from the 8th Karuizawa Workshop on Circuits and Systems)
- Category
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Takao ONOYE, Toshihiro MASAKI, Yasuo MORIMOTO, Yoh SATO, Isao SHIRAKAWA, Kenji MATSUMURA, "Single Chip Implementation of MPEG2 Decoder for HDTV Level Pictures" in IEICE TRANSACTIONS on Fundamentals,
vol. E79-A, no. 3, pp. 330-338, March 1996, doi: .
Abstract: A single chip MPEG2 MP@HL Video decoder has been developed, which consists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip frame memories and the interfaces associated with it. Owing to sophisticated I/O interfaces among functional units, the macroblock level pipeline in conjunction with different decording facilities attains a high throughput to such an extent as to decode HDTV images in real time. Moreover, a set of these functional units, pipeline buffers, and frame memory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e79-a_3_330/_p
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@ARTICLE{e79-a_3_330,
author={Takao ONOYE, Toshihiro MASAKI, Yasuo MORIMOTO, Yoh SATO, Isao SHIRAKAWA, Kenji MATSUMURA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Single Chip Implementation of MPEG2 Decoder for HDTV Level Pictures},
year={1996},
volume={E79-A},
number={3},
pages={330-338},
abstract={A single chip MPEG2 MP@HL Video decoder has been developed, which consists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip frame memories and the interfaces associated with it. Owing to sophisticated I/O interfaces among functional units, the macroblock level pipeline in conjunction with different decording facilities attains a high throughput to such an extent as to decode HDTV images in real time. Moreover, a set of these functional units, pipeline buffers, and frame memory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Single Chip Implementation of MPEG2 Decoder for HDTV Level Pictures
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 330
EP - 338
AU - Takao ONOYE
AU - Toshihiro MASAKI
AU - Yasuo MORIMOTO
AU - Yoh SATO
AU - Isao SHIRAKAWA
AU - Kenji MATSUMURA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E79-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1996
AB - A single chip MPEG2 MP@HL Video decoder has been developed, which consists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip frame memories and the interfaces associated with it. Owing to sophisticated I/O interfaces among functional units, the macroblock level pipeline in conjunction with different decording facilities attains a high throughput to such an extent as to decode HDTV images in real time. Moreover, a set of these functional units, pipeline buffers, and frame memory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8
ER -
English
