A single chip MPEG2 MP@HL Video decoder has been developed, which consists mainly of specific functional units and macroblock level pipeline buffers. A new organization is also devised for a set of off-chip frame memories and the interfaces associated with it. Owing to sophisticated I/O interfaces among functional units, the macroblock level pipeline in conjunction with different decording facilities attains a high throughput to such an extent as to decode HDTV images in real time. Moreover, a set of these functional units, pipeline buffers, and frame memory interfaces, together with a sequence controller, is integrated for the first time in a single chip, which has the total area of 8.8 9.2mm2 with a 0.6µm triple-mental CMOS technology, and dissipates 1.2 W from a single 3.3 V supply.