IEICE TRANSACTIONS on Fundamentals
High-Level Synthesis of a Multithreaded Processor for Image Generation
Summary :
The design procedure of a multithreaded processor dedicated to the image generation is described, which can be achieved by means of a high-level synthesis tool PARTHENON. The processor employs a multithreaded architecture which is a novel promising approach to the parallel image generation. This paper puts special stress on the high-level synthesis scheme which can simplify the behavioral description for the structure and control of a complex hardware, and therefore enables the design of a complicated mechanism for a multithreaded processor. Implementation results of the synthesis are also shown to demonstrate the performance of the designed processor. This processor greatly improves the throughput of the image generation so far attained by the conventional approach.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E78-A No.3 pp.322-330
- Publication Date
- 1995/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section of Selected Papers from the 7th Karuizawa Workshop on Circuits and Systems)
- Category
- VLSI Design Technology and CAD
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Takao ONOYE, Toshihiro MASAKI, Isao SHIRAKAWA, Hiroaki HIRATA, Kozo KIMURA, Shigeo ASAHARA, Takayuki SAGISHIMA, "High-Level Synthesis of a Multithreaded Processor for Image Generation" in IEICE TRANSACTIONS on Fundamentals,
vol. E78-A, no. 3, pp. 322-330, March 1995, doi: .
Abstract: The design procedure of a multithreaded processor dedicated to the image generation is described, which can be achieved by means of a high-level synthesis tool PARTHENON. The processor employs a multithreaded architecture which is a novel promising approach to the parallel image generation. This paper puts special stress on the high-level synthesis scheme which can simplify the behavioral description for the structure and control of a complex hardware, and therefore enables the design of a complicated mechanism for a multithreaded processor. Implementation results of the synthesis are also shown to demonstrate the performance of the designed processor. This processor greatly improves the throughput of the image generation so far attained by the conventional approach.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e78-a_3_322/_p
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@ARTICLE{e78-a_3_322,
author={Takao ONOYE, Toshihiro MASAKI, Isao SHIRAKAWA, Hiroaki HIRATA, Kozo KIMURA, Shigeo ASAHARA, Takayuki SAGISHIMA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Level Synthesis of a Multithreaded Processor for Image Generation},
year={1995},
volume={E78-A},
number={3},
pages={322-330},
abstract={The design procedure of a multithreaded processor dedicated to the image generation is described, which can be achieved by means of a high-level synthesis tool PARTHENON. The processor employs a multithreaded architecture which is a novel promising approach to the parallel image generation. This paper puts special stress on the high-level synthesis scheme which can simplify the behavioral description for the structure and control of a complex hardware, and therefore enables the design of a complicated mechanism for a multithreaded processor. Implementation results of the synthesis are also shown to demonstrate the performance of the designed processor. This processor greatly improves the throughput of the image generation so far attained by the conventional approach.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - High-Level Synthesis of a Multithreaded Processor for Image Generation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 322
EP - 330
AU - Takao ONOYE
AU - Toshihiro MASAKI
AU - Isao SHIRAKAWA
AU - Hiroaki HIRATA
AU - Kozo KIMURA
AU - Shigeo ASAHARA
AU - Takayuki SAGISHIMA
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E78-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1995
AB - The design procedure of a multithreaded processor dedicated to the image generation is described, which can be achieved by means of a high-level synthesis tool PARTHENON. The processor employs a multithreaded architecture which is a novel promising approach to the parallel image generation. This paper puts special stress on the high-level synthesis scheme which can simplify the behavioral description for the structure and control of a complex hardware, and therefore enables the design of a complicated mechanism for a multithreaded processor. Implementation results of the synthesis are also shown to demonstrate the performance of the designed processor. This processor greatly improves the throughput of the image generation so far attained by the conventional approach.
ER -
English
