IEICE TRANSACTIONS on Fundamentals
Prescaler PLL Frequency Synthesizer with Multi-Programmable Divider
Summary :
In the phase locked loop (PLL) frequency synthesizer which is used in a higher frequency region, the prescaler method is employed in order to increase the operating frequency of the programmable divider. However, since the fixed divider whose division ratio is same as the prescaler is installed at the following stage of the reference divider, the reference frequency is decreased and the performance of the PLL frequency synthesizer is degraded. The prescaler PLL frequency synthesizer using multi-programmable divider is one of the counter measures answering the request. In this paper we propose the reduction of the number of programmable dividers by using the (N+1/2) programmable divider. The effectiveness of the proposed method is confirmed by experimental results.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.3 pp.421-426
- Publication Date
- 2000/03/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section of Selected Papers from the 12th Workshop on Circuits and Systems in Karuizawa)
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Yasuaki SUMI, Shigeki OBOTE, Naoki KITAI, Hidekazu ISHII, Ryousuke FURUHASHI, Yutaka FUKUI, "Prescaler PLL Frequency Synthesizer with Multi-Programmable Divider" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 3, pp. 421-426, March 2000, doi: .
Abstract: In the phase locked loop (PLL) frequency synthesizer which is used in a higher frequency region, the prescaler method is employed in order to increase the operating frequency of the programmable divider. However, since the fixed divider whose division ratio is same as the prescaler is installed at the following stage of the reference divider, the reference frequency is decreased and the performance of the PLL frequency synthesizer is degraded. The prescaler PLL frequency synthesizer using multi-programmable divider is one of the counter measures answering the request. In this paper we propose the reduction of the number of programmable dividers by using the (N+1/2) programmable divider. The effectiveness of the proposed method is confirmed by experimental results.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_3_421/_p
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@ARTICLE{e83-a_3_421,
author={Yasuaki SUMI, Shigeki OBOTE, Naoki KITAI, Hidekazu ISHII, Ryousuke FURUHASHI, Yutaka FUKUI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Prescaler PLL Frequency Synthesizer with Multi-Programmable Divider},
year={2000},
volume={E83-A},
number={3},
pages={421-426},
abstract={In the phase locked loop (PLL) frequency synthesizer which is used in a higher frequency region, the prescaler method is employed in order to increase the operating frequency of the programmable divider. However, since the fixed divider whose division ratio is same as the prescaler is installed at the following stage of the reference divider, the reference frequency is decreased and the performance of the PLL frequency synthesizer is degraded. The prescaler PLL frequency synthesizer using multi-programmable divider is one of the counter measures answering the request. In this paper we propose the reduction of the number of programmable dividers by using the (N+1/2) programmable divider. The effectiveness of the proposed method is confirmed by experimental results.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Prescaler PLL Frequency Synthesizer with Multi-Programmable Divider
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 421
EP - 426
AU - Yasuaki SUMI
AU - Shigeki OBOTE
AU - Naoki KITAI
AU - Hidekazu ISHII
AU - Ryousuke FURUHASHI
AU - Yutaka FUKUI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E83-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2000
AB - In the phase locked loop (PLL) frequency synthesizer which is used in a higher frequency region, the prescaler method is employed in order to increase the operating frequency of the programmable divider. However, since the fixed divider whose division ratio is same as the prescaler is installed at the following stage of the reference divider, the reference frequency is decreased and the performance of the PLL frequency synthesizer is degraded. The prescaler PLL frequency synthesizer using multi-programmable divider is one of the counter measures answering the request. In this paper we propose the reduction of the number of programmable dividers by using the (N+1/2) programmable divider. The effectiveness of the proposed method is confirmed by experimental results.
ER -
English
