IEICE TRANSACTIONS on Fundamentals
Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation
Summary :
In this paper, an architecture of multi-threaded processor for embedded systems is proposed and evaluated comparing with other processors for embedded systems. The experimental results show the trade-off of hardware costs and execution times among processors. Taking proposed multi-threaded processor into account as an embedded processor, design space of embedded systems are enlarged and more suitable architecture can be selected under some design constraints.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E84-A No.3 pp.748-754
- Publication Date
- 2001/03/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section of Selected Papers from the 13th Workshop on Circuits and Systems in Karuizawa)
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Shinsuke KOBAYASHI, Yoshinori TAKEUCHI, Akira KITAJIMA, Masaharu IMAI, "Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation" in IEICE TRANSACTIONS on Fundamentals,
vol. E84-A, no. 3, pp. 748-754, March 2001, doi: .
Abstract: In this paper, an architecture of multi-threaded processor for embedded systems is proposed and evaluated comparing with other processors for embedded systems. The experimental results show the trade-off of hardware costs and execution times among processors. Taking proposed multi-threaded processor into account as an embedded processor, design space of embedded systems are enlarged and more suitable architecture can be selected under some design constraints.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e84-a_3_748/_p
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@ARTICLE{e84-a_3_748,
author={Shinsuke KOBAYASHI, Yoshinori TAKEUCHI, Akira KITAJIMA, Masaharu IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation},
year={2001},
volume={E84-A},
number={3},
pages={748-754},
abstract={In this paper, an architecture of multi-threaded processor for embedded systems is proposed and evaluated comparing with other processors for embedded systems. The experimental results show the trade-off of hardware costs and execution times among processors. Taking proposed multi-threaded processor into account as an embedded processor, design space of embedded systems are enlarged and more suitable architecture can be selected under some design constraints.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Proposal of a Multi-Threaded Processor Architecture for Embedded Systems and Its Evaluation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 748
EP - 754
AU - Shinsuke KOBAYASHI
AU - Yoshinori TAKEUCHI
AU - Akira KITAJIMA
AU - Masaharu IMAI
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E84-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 2001
AB - In this paper, an architecture of multi-threaded processor for embedded systems is proposed and evaluated comparing with other processors for embedded systems. The experimental results show the trade-off of hardware costs and execution times among processors. Taking proposed multi-threaded processor into account as an embedded processor, design space of embedded systems are enlarged and more suitable architecture can be selected under some design constraints.
ER -
English
