A modern system-on-chip (SoC) includes many heterogeneous IP components. Generally, a few embedded processors are integrated into SoCs. An asynchronous circuit design technique is employed to achieve low power/energy consumption. In this paper, we design an asynchronous embedded processor on FPGAs and analyze its possible benefits on commercial FPGAs. We use commercially available 65nm high-performance Virtex-5 and 45nm low-power Spartan-6 Xilinx FPGAs to show the impact on power consumption for the two different extreme cases. For the high performance Virtex-5, our asynchronous processor shows 36.8% lower power consumption when compared with its synchronous counterpart. On the other hand, the asynchronous processor consumes 25.6% more power in a low power Spartan-6 FPGA. However, through simple analysis and power simulation, we show that the event-driven nature of asynchronous circuits can further save power/energy even in the Spartan-6 FPGA.

This paper presents a new asynchronous FIFO design to reduce forward latency in a linear structure. The operation mode for each cell can be reconfigured dynamically as either of the two schemes, wave pipelining or handshaking, according to the data flow in the FIFO. The adoption of wave pipelining to the conventional self-timed FIFO can reduce the overhead of the handshaking as well as latching control in each stage. Initial pre-layout simulations indicate about two times of improvement on latency performance over a state-of-art asynchronous FIFO, while retaining its throughput.

This paper presents the Coloured Petri Net modeling for security analysis of the Extended Role Based Access Control systems.

Although many successful asynchronous control circuit synthesis methods are available, it is still unwieldy to conceive and describe the behaviors of a number of controllers which constitute a control unit of a target system manually. In this paper, an automatic and systematic method to derive an efficient asynchronous control unit from a system specification, a control data flow graph (CDFG), is suggested. In order to acquire an asynchronous control unit of acceptable quality, a new process-oriented method is proposed. In this method, the resulting asynchronous control unit has complete separation of 'execution controllers' and 'execution order controllers' according to the hierarchical decomposition of a given CDFG. This distributive feature leads to a significant improvement in area, performance, implementability and synthesis time for the derived asynchronous control units.

A multiple-issue on-chip bus of a layered architecture in a Globally Asynchronous Locally Synchronous (GALS) design style, supporting in-order/out-of-order completion, is proposed in this letter. The throughput of the proposed on-chip bus is increased by 31.3% and 34.3%, while power consumption overhead is only 6.76% and 3.98%, respectively, as compared to an asynchronous single-issue on-chip bus.

Inter-domain communications on a chip require a synchronizer to resolve the timing problems between an input and a clock of a destination. This paper presents a parallel flop synchronizer and its interface circuit for transferring asynchronous data to the clock domain. The proposed scheme uses a bank of independent two-flops in parallel and supports a two-phase handshake protocol. Compared to the conventional two-flop synchronizer, performance analysis shows that the proposed scheme can reduce latency up to one and a half of clock cycles while retaining its safety to a tolerable level. All designs have been implemented in a 0.25 µm CMOS technology to verify performance analysis of the proposed synchronization.

A mutated adder architecture utilizing a mixture of carry propagation schemes is proposed to design a delay-area efficient adder which were not available in an ordinary design space. Further, we develop an optimization method based on integer linear programming to search the expanded design space of the mutated adder.

In this paper, we propose a new design technique called extit{asynchronous multi-frequency clocking} for suppressing EMI at a chip design level by combining two independent EMI-suppressing approaches: extit{multi-frequency clocking} and extit{asynchronous circuit design} techniques. To show the effectiveness of our approach, a five-stage pipelined asynchronous MIPS with multi-frequency clocking has been implemented on a commercial Xilinx FPGA device. Our approach shows 11.05 dB and 5.88 dB reductions of peak EM radiation in the prototyped implementation when compared to conventional synchronous and bundled-data asynchronous circuit counterparts, respectively.

Since the inception of Globally Asynchronous Locally Synchronous (GALS) VLSI design, GALS has been considered a promising design technique for multi-clock-domain System-on-Chip (SoC). Among the handshake protocols available for SoC design, delay insensitive (DI) handshake protocol is becoming a core technology, since it facilitates robust data transfer regardless of wire delay variation. In this paper, a new data encoding scheme Differential Value Encoding (DVE) is proposed for two-phase 1-of-N DI handshake protocol. Compared with the conventional data encoding method, the proposed scheme effectively reduces the crosstalk effect on wires sending sequentially increasing data patterns, resulting in reduction of the data transfer time. Simulation results with SPEC CPU 2000 benchmarks and sequentially increasing data pattern reveal that the DVE scheme can reduce the crosstalk effect by tens of percentage and significantly decrease the data transfer time.

In this paper, we propose an approach to test pattern generation for Speed-Independent (SI) asynchronous control circuits. Test patterns are generated based on a specified sequence, which is derived from the specification of a target circuit in the form of a Signal Transition Graph (STG). Since the sequence represents the behavior of a circuit only with stable states, the state space of the circuit can be represented as reduced one. A product machine, which consists of a fault-free circuit and a faulty circuit, is constructed and then the specified sequence is applied sequentially to the product machine. A fault is detected when the product machine produces inconsistency, i.e., output values of a fault-free circuit and a faulty circuit are different, and the sequentially applied part of the sequence becomes a test pattern to detect the fault. We also propose a test generation method using an undetectable fault identification as well as the specified sequence. Since the reduced state space is a subset of that of a gate level implementation, test patterns based on a specification cannot detect some faults. The proposed method identifies those faults with a circuit topology in advance. BDD is used to implement the proposed methods efficiently, since the proposed methods have a lot of state sets and set operations. Experimental results show that the test generation using a specification achieves high fault coverage over single stuck-at fault model for several synthesized SI circuits. The proposed test generation using a circuit topology as well as a specification decreases execution time for test generation with negligible cost retaining high fault coverage.

This letter presents a synchronizer and its handshake interface for bridging clock domains in SoC. The proposed scheme uses a double two-flop synchronizer operated at different clock edges respectively, based on a two-phase handshake protocol. Performance analysis shows that the proposed design reduces latency up to a clock cycle, while retaining its safety to a tolerable level.

In this paper, we develop asymptotic analysis and simulation models to better understand the characteristics of performance and energy consumption in a multi-core processor design in which dynamic voltage scaling is used. Our asymptotic model is derived using Amdahl's law, Rent's rule and power equations to derive the optimum number of cores and their voltage levels. Our model can predict the possible impact of different multi-core processor configurations on the performance and energy consumption for given workload characteristics (e.g. available parallelism) and process technology parameters (e.g. ratios of dynamic and static energies to total energy). Through the asymptotic analysis and optimization based on the models, we can observe an asymptotic relationship between design parameters such as "the number of cores," "core size" and "voltage scaling strategies" of a multi-core architecture with regards to performance and energy consumption at an initial phase of the design.

In this paper, we propose a new user-level file system to support block relocation by modifying the file allocation table without actual data copying. The key idea of the proposed system is to provide the block insertion and deletion function for file manipulation. This approach can be used very effectively for block-aligned file modification applications such as a compress utility and a TAR archival system. To show the usefulness of the proposed file system, we adapted the new functionality to TAR application by modifying TAR file to support an efficient sub-file management scheme. Experiment results show that the proposed system can significantly reduce the file I/O overhead and improve the I/O performance of a file system.